DaVinci Genlock

Each video input capture port can be operated as one 16-bit input channel (with separate Y and Cb/Cr inputs) or two clock independent 8-bit input channels (with interleaved Y/C data input).

For each VIP instance, two pixel clock input domains are supported (Port A and Port B). The two pixel clock input domains can be individually configured in any combination of embedded sync or discrete sync.

Regards,

Pavel

Jed,

This is not possible. Even if its possible, then it can cause lot of other side effects, I believe.

Thanks Pavel, but can I use one of those input clock domains to drive the video output?  In other words, can I feed a video signal into the chip, and then drive it back out again with the same clocks and syncs such that no frames are lost?

Thanks,

Jed

Hi,

Its not possible to drive outputs using external clock. But what you can do is that if you have some kind of FPGA for sending YUV signal to VIP, you can driver that FPGA using output clocks.

I came across a PPT slide that describes a Netra Genlock with a software PLL.  Has this been implemented?  See below: