C6678 TSIP "Far end loopback"

Arnaud Maye

Hello,

Would anyone know if one can configure electrically connect TSIP0 and TSIP1 in order to have a "Far end loopback". We were considering to implement the connection in FPGA IOs without to care about the protocol. This would be same as soldering wires between both TSIP peripheral.

Is it something allowed, would that work?

Thank you,

Arnaud

over 12 years ago

0 Bill Taboada over 12 years ago

TI__Mastermind 42545 points

Hi Arnaud,

You can connect the transmit and receive data from TSIP0 to the receive and transmit data from TSIP1 to create a loopback but you would still have to provide a clock and frame sync from some external source. The TSIP can't be configured to drive clock and frame sync.

Regards, Bill

0 Arnaud Maye over 12 years ago in reply to Bill Taboada

Intellectual 400 points

Hello Bill,

Thank you for this answer. It is no problem for us to take care of clock/sync in the FPGA. Great news!!

Best Regards,

Arnaud

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C6678 TSIP "Far end loopback"