I am using McBSP for communication with serial ADC and DAC in order to implement half duplex modem on DSP part of the OMAP-L138. Only ADC or DAC is operating at the same time, but both are connected to the same McBSP channel. I am using McBSP FIFO and EDMA. I was using the same configuration for long time (almost a year) and everything was fine. The following sequence is used in order to switch between transmission and reception:
- Set McBSP settings to default (including setting SPCR to 0).
- Configure new settings
- Set FIFO settings
- Release McBSP from reset
My McBSP configuration for reception is:
XCR = 0x00020040
RCR = 0x00020020
SRGR = 0x300E0C05
PCR = 0x00000D05
SPCR = 0x03E20001
McBSP is clocked by 144MHz clock from PLL1.
Recently I had to change the polarity of the clock by setting PCR = 0x00000D04. Once I've changed this setting, I've started facing the following issue: once in a while after many TX-RX switches, the McBSP got stuck in some strange state. After starting the reception RFULL flag is set, (RSYNCERR is sometimes set) but no data is passed to FIFO (FIFO level shows 0) and of course no data is passed to DMA. Resetting the McBSP and setting all the configuration from the beginning does not help - the same situation is happening again. Stopping the device with debugger and reading McBSP registers releases the module from this freezing state, and it seems the only way to solve this situation (other than reset). I even tried turning off the clock to McBSP module, but it seems that this procedure is also freezing in the middle (during PTSTAT register polling for power state change).
I would appreciate any help in solving this issue.
Thanks,
Alexey