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C64x+ atomic operations on C6474?

Michael P
Expert 1810 points

Does the C6474 support the atomic operation primitives that are described in SPRU732J section 9 (LL-SL-CMTL)?

If so, are there constraints on the address(es) that are used with these instructions, or any constraints on other nearby instructions (beyond the rules mentioned in SPRU732 about only the .D2 unit being able to execute synchronization primitives, only one being allowed per execution packet, and the sequencing of the synchronization primitives)?

The source code from the IPC RTSC package (ipc_1_24_03_32/packages/ti/sdo/ipc/gates/GateAAMonitor_asm.s64P) mentions some megamodule errata, but I can't find the "GEM DATA MEMORY CONTROLLER" document it mentions, so I'm not sure if they apply to the C6474.

  • 0
    TI__Mastermind 30825 points

    No, that's only supported in the shared memory of the C6472 and TCI6486.  Please note that Atomic instructions tend to be used for Semaphore type operations, and the C6474 has a Hardware Semaphore block as opposed to implementing the LL/SL/CMTL.

    Best Regards,

    Chad