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EMIF Async with FPGA address line problem

Don Sacilowski1
Prodigy 90 points
Other Parts Discussed in Thread: OMAPL138

Hi all,

 We have made much progress in working with the OMAPl138 processor communications with a spartan-6 FPGA via the EMIF bus. Heres what we have:

 - We use address lines EMA_A[13:0]

- We are doing 16-bit addressing which will disable BA0

- I map the ASYNC2 address + 0x3800 using mmap_device_memory

- I write data to the pointer resulting from the mmap_device_memory call.

- On the FPGA we are using chipScope to look at address lines  EMA_A[13:0]

- What we see is 0x0E00 on the address lines where i would expect to see 0x3800. It's 2 bits off. ie. if I shift 0x0E00 to the left by 2 bits I get 0x3800.

- If I change my address to be mapped to ASYNC2 address + 0xE000 (0x3800 shifted left by 2 bits), chipScope sees 0x3800.

All the timing looks good as far as setup, read and write wait cycles goes. Also, the data comes over correctly.

I think I may be missing something in the setup somewhere - any thoughts?

  • 0
    Expert 1950 points

    Hello,

    See EMIFA User's Guide: in asynchronous mode, the EMA_A[22:0] bus make an address for 32-bit words, while BA[1:0] extend the address bus for 8- & 16- bit peripherals. The two "shifting" lines are then BA0 and BA1. EMA_A[22:0] always reflect bits 24:2 of CPU address registers, whatever the EMIFA 8/16/32-bit mode is.

  • 0
    Prodigy 70 points

    Hi Don Sacilowski1,

     I want to use EMIF-A interface on the omapl138 to connect the fpga.  the dsp subsystem read or write data in FIFO, then dsp conmunication with arm by  mpcsxfer project (a sample in dsplink  source). Did you use dsplink to make the two processors to comunication in your work? Can you give me some advices about how to use emifa port to read data in dsplink samples?

    Tks!