Syslink does not power down OMAP3621.
After "slaveloader powerup DSP" followed by "slaveloader powerdown DSP" CM_CLKSTST_IVA2 is 0x1 and PM_PWSTST_IVA2 is 0xFF7.
What is the way to solve the problem?
Thanks,
Igor
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Syslink does not power down OMAP3621.
After "slaveloader powerup DSP" followed by "slaveloader powerdown DSP" CM_CLKSTST_IVA2 is 0x1 and PM_PWSTST_IVA2 is 0xFF7.
What is the way to solve the problem?
Thanks,
Igor
Hi Igor,
Which version of SysLink are you using? Are you using the code as is or have you modified it? We expect the code for the OMAP3530 to work on the OMAP3621. Did you insmod syslink.ko with TRACE=1 and TRACEFAILURE=1 to see if there were any errors?
Best regards,
Vincent
Hi Vincent,
I use syslink_2_21_00_03.
Although we used a slightly modified syslink, I tried the original one with exactly the same result.
I loaded the driver with TRACE=1 and TRACEFAILURE=1 and saw no errors.
Any ideas?
Thanks,
Igor
Hi Igor,
I am in the process of reproducing the same on OMAP3530. In the meantime, how are you accessing these registers? Did you create a separate utility program to print these out independently, or did you simply print them by modifying SysLink?
-Vincent
Hi Vincent,
I created a tiny kernel module that "ioremap"s a couple of pages and prints the values of the registers. If it can help you, please e-mail me and I will send it to you.
Thanks,
Igor
Vincent,
Could you please explain me why OMAP3530PWR_off turns IVA2 on-off-on-off?
I have a simple power-off sequence that does the job somehow (bellow). Could you please compare it with OMAP3530PWR_off and tell me what the right sequence should look like?
Thanks,
Igor
------------
PM_WKDEP_IVA2 = 0;
PRM_IRQENABLE_IVA2 = 0;
CM_CLKSTCTRL_IVA2 = 0;
CM_CLKEN_PLL_IVA2 = 7;
CM_FCLKEN_IVA2 = 1;
RM_RSTCTRL_IVA2 |= 7;
CM_FCLKEN_IVA2 = 0;
for (i = 0; (CM_IDLEST_PLL_IVA2 & 1) == 0; i ++) {
if (i >= 5000) {
printk (KERN_ERR "Fail %u\n", __LINE__);
return 0;
}
udelay (1);
}
RM_RSTST_IVA2 |= 7 << 8;
RM_RSTCTRL_IVA2 = 0;
for (i = 0; RM_RSTST_IVA2 & (7 << 8); i ++) {
if (i >= 5000) {
printk (KERN_ERR "Fail %u\n", __LINE__);
return 0;
}
udelay (1);
}
CM_FCLKEN_IVA2 = 1;
RM_RSTCTRL_IVA2 |= 7;
CM_FCLKEN_IVA2 = 0;
for (i = 0; (CM_IDLEST_PLL_IVA2 & 1) == 0; i ++) {
if (i >= 5000) {
printk (KERN_ERR "Fail %u\n", __LINE__);
return 0;
}
udelay (1);
}
RM_RSTST_IVA2 |= 7 << 8;
RM_RSTCTRL_IVA2 = 0;
for (i = 0; RM_RSTST_IVA2 & (7 << 8); i ++) {
if (i >= 5000) {
printk (KERN_ERR "Fail %u\n", __LINE__);
return 0;
}
udelay (1);
}
PM_PWSTCTRL_IVA2 &= ~3;
CM_CLKSTCTRL_IVA2 = 1;
for (i = 0; PM_PWSTST_IVA2 & 0xff7; i ++) {
if (i >= 5000) {
printk (KERN_ERR "Fail %u\n", __LINE__);
return 0;
}
udelay (1);
}
CM_CLKSTCTRL_IVA2 = 0;
CM_CLKEN_PLL_IVA2 = 1;
printk (KERN_ERR "RM_RSTST_IVA2: %X\n", RM_RSTST_IVA2);
printk (KERN_ERR "PM_PWSTST_IVA2: %X\n", PM_PWSTST_IVA2);
printk (KERN_ERR "CM_CLKSTST_IVA2: %X\n", CM_CLKSTST_IVA2);
Hi Igor,
It turns out this is a known issue. We'll need some time to investigate on the fix - maybe we'll end up doing the same thing as what you are already doing. We'll keep you posted once we have got this resolved.
Best regards,
Vincent
Hi Igor,
Judging from the work load our development team has at the moment, it will be at least several months before we could get to it. Given you seem to have found a sequence that does the job, it may be best if you stick to it for now. Sorry I don't have better news for you.
Best regards,
Vincent
Hi Vincent,
I would like to know the answer for the following questions.
Power sequence related questions.
1. Why do you turn IVA2 on-off-on-off, using "force mode" for the fist transition to "off" state and "auto mode" for the second transition to "off" state?
2. Why do you turn IVA2 off first when you need to turn it on?
3. Why do you assert RST2_IVA2 and RST1_IVA2 (register RM_RSTCTRL_IVA2) separately in a seuqnce?
4. Why does it work when I do reset 2 times (see my sequnece)?
5. Why do you zero boot vector and set boot mode to 1 while turning IVA2 off?
6. During reset, the board somtimes hangs, if I set IVA2 DPLL to "bypass mode" and everything goes OK, if
the DPLL is set to "lock mode". Any explanation?
Related questions:
1. Is it OK to swicth between DPLL modes in the DSP code? Is it OK to change the deviders in the DSP code?
If so, how should I proceed?
2. Could such reprogramming cause IVA2's IOMMU failure (I saw it once)?
Thanks,
Igor
Hi Igor,
Given you are after the correct power sequence, I'd suggest you direct your query to the OMAP35x hardware forum (http://e2e.ti.com/support/dsp/omap_applications_processors/f/447.aspx). The reality is that the code you are looking at was handled years ago by another team (which is no longer around), so we'll have to invest significant time to revalidate it, and our hands are tied at the moment. Therefore if you are in a rush it may be best if you work directly with the hardware team to get the correct power sequence from them.
Best regards,
Vincent