Sys Bios Interrupt Life Cycle

Brian Sarvis

Hello,

I'm wondering if the attached also explains what happens in Sys/Bios during a hardware interrupt (HWI). Based on it, the total worst-case time outside of an interrupted function (provided there are no other context switches) would be the latency + prologue + ISR execution time + epilogue. Have I missed anything?

In a benchmark HTML file for the C64p, it lists prologue time, epilogue time, and dispatch time. The dispatch time is smaller than the sum of the prologue and epilogue times. Why the three different quoted times?

I'll see if I can attach the latency document in a separate post.

Thanks.

Brian Sarvis

Sys/Bios 6_33_05_46

XDC 3_23_03_53

CCS Version: 5.2.1.00018

spraax9 Explanation of raw vs DSP BIOS interrupt handling latency.pdf

over 12 years ago

0 Brian Sarvis over 12 years ago

Prodigy 160 points

C64p latencies added.

0 judahvang over 12 years ago

TI__Mastermind 32475 points

Brian,

Yes, the doc describes the options you have for processing a HWI in BIOS. I think your understanding of the total worst case time is correct.

Even though the dispatch time is slightly smaller than the sum of the prologue and epilogue this is simply due to clock cycles on the C6000. They are equivalent.

Now why all three are quoted...I'm not sure about this, but I assume someone asked for all three.

Judah

Processors

Processors forum

Sys Bios Interrupt Life Cycle