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C6424 INTERR with SYS/BIOS

Brian Sarvis
Prodigy 160 points

Hello,

I started a thread in the SYS/BIOS section, but it was suggested I post this question here.

In SPRU871K, section 7.5.3.4, the dropped interrupt mask register is described (INTDMASK).  It is listed as read-only.  That seems very strange, and when I write to it, and read it back, I get what I wrote.  So, it seems the register is writeable.  Is this just a misprint?

More importantly, I'd like to generate an error anytime any interrupt is missed - either because the ISR takes too long, or because interrupts are held off.  I'm generating interrupts with the McBSP, and I see them regularly on an oscilloscope, triggered by an unused GPIO pin in the ISR (the execution graph is too slow in this application).  Then, I create a very crude interruption in the hardware interrupt processing by using the Hwi_disable() function. 

When I do this, I do not get an INTERR interrupt, nor do I see any change in the INTXSTAT register.  I've tried most all the masking permutations in SYS/BIOS (MaskingOption_ALL to NONE).  They all fail to produce a result.  What am I missing?

Thanks.

Brian Sarvis

 

  • 0
    TI__Guru* 84110 points

    Brian,

    Apparently, nobody knows the answer to your question. Sorry it has been a month with no response.

    To your first question, please see Table 7-16 in SPRU871K for additional information on INTDMASK's permissions. Our documentation is a bit confusing in Figure 7-40, to say the least, which is why you asked. So INTDMASK is writable in Supervisor mode.

    To your second question, my guess is that the Hwi_disable() function inhibits the missed interrupt flag from being set. Instead of doing that, setup another ISR that includes a long delay and see if that will work better. But I am not sure what exactly it takes to set the missed interrupt flag. But if you can try this test, and it does not work either, we can come up with another idea.

    Regards,
    RandyP