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DSP Cycles consumed by Cache_Inv()

Jeeva Raj Arumugam
Prodigy 80 points

How much cycles will be consumed for Cache invalidation using Cache_Inv() for 1KB of data in SL2? and will it be proportional for even 512KB of data invalidation?

is there any maximum limit for the amount of bytes can be invalidated in one call?

  • 0
    TI__Mastermind 32475 points

    Hi,

    You didn't specify which device you are looking at.  Whether its a C64+, C674, or C66 device.
    Here are some unofficial numbers for the C6472 device:

    Size,  Memory,   wait,   L1D size,   L2 size,   Time

    64B,  SL2,   wait, L1D 32K, L2 64K: Time = 243
    64B,  SL2, nowait, L1D 32K, L2 64K: Time = 142
    256B, SL2,   wait, L1D 32K, L2 64K: Time = 295
    256B, SL2, nowait, L1D 32K, L2 64K: Time = 147
    4KB,  SL2,   wait, L1D 32K, L2 64K: Time = 1669
    4KB,  SL2, nowait, L1D 32K, L2 64K: Time = 150
    16KB, SL2,   wait, L1D 32K, L2 64K: Time = 6144
    16KB, SL2, nowait, L1D 32K, L2 64K: Time = 148

    I don't have 1KB number but it should fall somewhere between 256B and 4KB.  I don't think you can say the timing are proportional with increasing sizes.

    You should be able to specify any size for the Cache_Inv().

    wait - this means wait for the invalidate operation to complete.

    no wait - this means issue the invalidate operation but do not wait for it to complete.

    Judah