OMAPL138 USB2.0 clock question

Jian Ma

Other Parts Discussed in Thread: OMAPL138

Hi,

The OMAPL138 USB2.0 subsystem can use AUXCLK as reference clock input. The AUXCLK sources from OSCIN. In that case, I can bypass the system PLL module to only use AUXCLK for USB2.0. I am confused why PLL0_SYSCLK2 is still needed for USB2.0. Any suggestions?

Thanks!

over 12 years ago

0 David (ASIC) Liu over 12 years ago

TI__Guru**** 177301 points

Jian

The AUXCLK is used to clock the USB PHY, the PLL0_SYSCLK2 is needed for the USB digital portion. The PLL0_SYSCLK2 must be greater than 30 MHz for
proper operation of the USB controller. A clock rate of 60 MHz or greater is recommended to avoid data throughput reduction.

Thanks

David

0 Jian Ma over 12 years ago in reply to David (ASIC) Liu

Intellectual 350 points

Hi David,

Thank you for the response.

Best,

Jian

0 Hock Leong Ang over 12 years ago in reply to Jian Ma

Intellectual 310 points

Hi David and All,

I would like to select USB2.0 clock source as PLL0_AUXCLK. May I know how to change the CFGCHIP2.USB0PHYCLKMUX bit (=1) and CFGCHIP2.USB1PHYCLKMUX (=0) at starterware OMAPL138_StarterWare_1_10_03_03?

Thank you very much.

0 David (ASIC) Liu over 12 years ago in reply to Hock Leong Ang

TI__Guru**** 177301 points

Hock

Under directory called 'tool', then'gel', there are the GEL files for OMAPL138_ARM, OMAPL138_DSP, and OMAPL138_LCDK, you can pick the right GEL file and modify the PLL configuration within the GEL file.

Have you got a chance to take a look at the Startware starting guide: http://processors.wiki.ti.com/index.php/StarterWare_Getting_Started_01.20.XX.XX#CCS_Help?

Thanks
David

0 Hock Leong Ang over 12 years ago in reply to David (ASIC) Liu

Intellectual 310 points

Hi David,

I am able to edit the parameter and my USB work now.

Thank you.

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OMAPL138 USB2.0 clock question