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The 2nd MAC can't receive.

Hi experts,

My board use Dual MAC mode. But I find the eth0 works well and eth1 can't receive. Receive interrupt never occured while I plug in the cable to eth1 interface. I can see ARP packets issue when I ping my host if I observe with wireshark. and I can see my host replied.

But limited by my poor background knowledge of network, I can't understand all the contents TRM provide in short time. So I think, Is there a simple way to check where it go wrong? Can I check some registers to find out the reason?

I read the ALE control register, and get the value 0x80000004. Is this the value should be? I searched the forum and someone said bit 4 of the register Bypass mode should be set. Does this cause failure to receive packets?

BTW, What is the ALE table in 14.3.2.7.1 of TRM? Is it a software structure or a memory region in the chip? I can't find the explanation of it.

regards,

Lihua

  • Problem solved.

    To use the 2nd MAC, we have to add a switch ontroled by gpio to swith CDS_DV as wait0 for the nand at boot time. I forgot to swith it to PHY after boot up.

  • Thanks for sharing your solution.

    AM335x Silicon Revision 2.0 and newer devices will provide two new additional pin multiplexing options for the RMII2_CRS_DV signal function.  So the switch you currently are using may not be needed when you switch to the new silicon revision.

    The first new terminal option will be mode2 of GPMC_CSn3.

    The second new terminal option will be mode 3 of GPMC_A9 (via a another level of pin multiplexing which provides the original MMC2_DAT7 signal or RMII2_CRS_DV signal when Mode3 is selected).

    You may want to keep this in mind if you are designing new PCBs.

    Regards,
    Paul

     

  • Thank you Paul, That is a good news.

  • I had the same problem, with the same solution. In my case, there was a problem with the chip I used to multiplex the nand and CRS_DV signal during and after boot.

  • Hi , lihua.

    my board use a EMAC mode. But, I find eth0 can't receive. receive interrupt never occured while I plug in the cable to eth0 interface. I can also see ARP packets issue when I ping my host if I observe with wireshark. and I can see my host replied.

    can you help me?

    regards.

     

  • I have the same problem , Could you please tell me how to fix it in code?Thanks for you reply.

  • OP had a physical problem that can't be fixed with code. On rev1 of the silicon there was a signal needed to boot from NAND that used the same pin as the CRS_DV signal needed to tell the MAC that it received a message.

    If you think you have the same problem as OP, check the CRS_DV signal going into the AM335x with an oscilloscope to make sure it pulses when you received a message. I used a MUX to switch a NAND signal and the CRS_DV signal. In my case, that MUX was broken.