C5505 CSL v. 3.01 PLL code

Todd Anderson78572

All:

I saw this on the previous CSL, and now I see it again here. In csl_pll.c,, function "getSysClk(void)" there is a huge section of code that is commented out, and at the end,

sysClk is returned with a value of 100 MHz. When I tried to uncomment the instructions, I received a compiler error. Is this going to be fixed?

over 13 years ago

0 Rahul Nair over 13 years ago

TI__Prodigy 225 points

Hi Todd,

We have already taken a note of this and will be fixed in future CSL release. In the meantime, replace the "getSysClk()" function in csl_pll.c file with the below given code:

#define CSL_PLL_CLOCKIN (32768u)

Uint32 getSysClk(void)
{
   Bool        pllRDBypass;
   Bool        pllOutDiv;
   Uint32    sysClk;
   Uint16    pllM;
   Uint16    pllRD;
   Uint16    pllOD;

   pllM = CSL_FEXT(CSL_SYSCTRL_REGS->CGCR1, SYS_CGCR1_M);

   pllRD = CSL_FEXT(CSL_SYSCTRL_REGS->CGCR2, SYS_CGCR2_RDRATIO);
   pllOD = CSL_FEXT(CSL_SYSCTRL_REGS->CGCR4, SYS_CGCR4_ODRATIO);

   pllRDBypass = CSL_FEXT(CSL_SYSCTRL_REGS->CGCR2, SYS_CGCR2_RDBYPASS);
   pllOutDiv   = CSL_FEXT(CSL_SYSCTRL_REGS->CGCR4, SYS_CGCR4_OUTDIVEN);

   sysClk = CSL_PLL_CLOCKIN;

   if (0 == pllRDBypass)
   {
       sysClk = sysClk/(pllRD + 4);
   }

   sysClk = (sysClk * (pllM + 4));

   if (1 == pllOutDiv)
   {
       sysClk = sysClk/(pllOD + 1);
   }

   /* Return the value of system clock in Hz */
   return(sysClk);
}

Hope this helps.

Regards,

Rahul Nair

0 Todd Anderson78572 over 13 years ago in reply to Rahul Nair

Guru 14640 points

Thanks,

As time permits, I will try this!

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C5505 CSL v. 3.01 PLL code