Is AHCLKR required for McASP in slaved I2S mode?

Hi Mike,

Per my understanding, you do not need to provide AHCLKR (high-frequency clock), if the ACLKR (bit clock, slower than AHCLKR) is fast enough for your use-case.

Check DM814x TRM, section 16.2.2 Clock and Frame Sync Generators:

The serial clock [ACLKR] (clock at the bit rate) may be sourced:
• Internally - by passing through two clock dividers off the internal clock source (AUXCLK). - in this case the clock is coming from the device PRCM
• Externally - directly from ACLKR/X pin, which are configured as inputs. In this case, the Rx/Tx high-speed clock logic [AHCLKR] is bypassed for the XCLK/RCLK generation.
• Mixed - an external high-frequency clock [AHCLKR] is input to the McASP on either the AHCLKX or AHCLKR pins, and divided down to produce the bit rate clock [ACLKR].
In the internal/mixed cases, the bit rate clock [ACLKR] is generated internally and should be driven out on the ACLKX (for transmit) or ACLKR (for receive) pins. In the internal case, an internally-generated high- frequency clock [AHCLKR] may be driven out onto the AHCLKX or AHCLKR pins to serve as a reference clock for other components in the system.
The McASP requires a minimum of a bit clock [ACLKR] and a frame sync [AFSR] to operate, and provides the capability to reference these clocks from an external high-frequency master clock [AHCLKR]. In DIT mode, it is possible to use only internally-generated clocks and frame syncs.

In one other E2E thread (about DSP, but I think the same is valid here) we have the following question and answer:

In which cases do I need the high speed AHCLKR?

Delta-sigma A/D converters oversample the signal (e.g. 256x or 384x the sampling frequency).  In these scenarios there is usually a high frequency clock [AHCLKR] corresponding to the oversampled signal in addition to the bit clock [ACLKR] and frame sync.  It's not absolutely required that the DSP provide all of these clocks, but with AHCLKR it is at least POSSIBLE (i.e. enables DSP to master the codec).  The way I've seen this implemented in the past with McBSP where we did not have the high speed clock interface was that we provided this high speed clock separately to the A/D (often using the CLKOUT pin by carefully selecting our CLKIN as 24.576 MHz or some other audio friendly frequency) and then the A/D converter would be setup as the master and it would divide down that high-speed clock to generate the other signals.

Here is one more thread, that might be in help:

http://e2e.ti.com/support/dsp/davinci_digital_media_processors/f/716/t/192708.aspx

Regards,

Pavel