Smart Reflex Testing using boundary scan control

Tim,

Which device are you using?

You may be able to download the BSDL file and look at the boundary scan chain implementation. I do not know how to interpret it, but you may be able to if you know enough about using boundary scan.

The VCNTLn pins all include an output attribute and an observe_only attribute, so it is likely that these pins cannot be set by EXTEST, but only read.

Doing what you describe could easily and likely take the CVDD voltage level out of the valid operating range for the device, and that could lead to the internal logic failing in a way that would invalidate any further results of your testing. That is a possible reason why this would not work, and if true it would be a good reason to design it to not allow this to work.

Regards,
RandyP

C6655 is the target device..  The  boundary cells will output during extest, the observe only cell is so you can readback what was written out.(if you tried writing a 1 but the pin was shorted to ground the readback would be 0 instead of 1)   The intention is only to confirm the power circuit is working.  After verification that the changing the dac inputs change the output voltage, then the dsp can be reset or power cycled to perform  other operations.

Tim,

If you are able to change the VCNTL pins with EXTEST, you still have the question of whether it could cause problems with the scan logic during those changes. Since that is not directly addressed in the documentation you and I have found, I will recommend against it until you get some other confirmation of this being a safe operation.

Please do note that you must follow the timing for the VCNTL pins as shown in the datasheet when you make any changes using EXTEST, should you decide to do that. The example you give in your initial post does not match the timing of the signals as shown in the datasheet.

Regards,
RandyP

Randy,

Yes I will need more documentation to understand the consequences of not meeting vcntl timing rules.   I believe the timing rules are specific to ensure that during core processing the power is at an optimum level.   During Extest, core logic is severed from the io pins.   I won't have any core logic faults using smart reflex power because the core logic is not being used.  My assumption would be that  the internal JTAG logic would use the 1.8 v for internal logic not the 1.5 v smart reflex power.  My concern would be thermal.  If there is not any processing and smart reflex power is held constant at the high smart reflex level for a couple seconds, will there be an issue where part damage could occur from over heating.   Timing of signal is not easily controlled by bscan,  It takes about 493  tcks on this device to change the state of an io pin (boundary reg is 487 cells,  plus movement in the jtag state machine from update DR through shift DR and back through  UpdateDR, (about 6tcks for state machine movement). So even if running at max tck of 30Mhz (33nS period) would result in 16 uS to toggle a pin via Extest.

Tim,

The datasheet shows the timing of the VCNTL pins as they will be presented to the SmartReflex power supply. If you do not follow that timing, the consequences will be determined by your SmartReflex power supply's response or lack of response.

Since I cannot confirm any of your assumptions, and my assumptions would be more conservative, I will let someone else jump in if they have other answers for you.

You must stay within the limits stated in the datsheet for both temperature and voltages, including the absolute maximums. Any operation outside the recommended operating conditions may be undefined.

Regards,
RandyP

Tim,

The concern raised by Randy is valid.  All logic including the boundary scan cells are on the AVS core logic supply.  The 1.8V supplies the output buffers only.  There is no guarantee of valid set-up and hold if the AVS CVDD supply is not at the desired level.  You can do the testing you desire but you must be supplying a CVDD supply from an external source while doing this testing.

The VCNTL output pins are controllable from BSCAN.  However, these are open drain outputs.  They cannot be driven high.  An external pull-up is needed to get them to go high.

Tom

Tom and Randy,

Thanks for your support.

Thanks for clarifying these are OD device and not driving active high.  

Is your concern that if I test the DAC to it highest output current (which will actually produce the lowest output voltage to CVDD) that the CVDD voltage will just be too low for valid operation of the core logic.

I don't necessary need to test the full range  of the DAC, that was just an example, I just want to test all the DAC inputs are properly connected.  I can use different test patterns to verify all vcntl pins are connected while maintaining a valid voltage at CVDD.

Or do you think I am violating timing rules to the DAC?

I do not believe I am violating and timing to the DAC.

We are using an LM10010 DAC and the Vcntl(2:0) need a min delay of 1 or 20 uS depending on rising and falling edge of vcntl3.

With BSAN we can stagger Vcntl2:0 with respect to Vcntl3 to meet these timing rules.

I am not sure why the c6655 datasheet specs a Max delay of 300nS.  That would violate the timing rules of most  DAC I have seen in this application??

I would not want to supply an external CVDD source to the DSP during Bscan Testing,  I am interested in verifying the operation of our smart reflex circuit during functional test under bscan control so externally powering CVDD would add no value.

Tim,

Yes, you could program the CVDD voltage too low for proper operation.  You can test at the high end of the voltage as long as you keep the chip temperature controlled.  Of course since you are operating in a BSCAN environment you will not have any clocks so your active power is zero.  This will help.  You will also be operating at an ambient room temperature.

DAC timing should not be an issue.  The 300ns delay is a skew max value between the VCNTL[3] strobe and the VCNTL[2:0] data bits.  This is a dual-phase data transfer that presents 3 bits at a time to create a 6 bit VID value.  KeyStone-I devices do not support a 4-bit VID mode.  You simply need to set the values on VCNTL[2:0] first and then toggle the VCNTL[3] strobe line.  The DAC will then latch the data bits.

I see that you are using the LM10010.  Now that the LM10011 is available we recommend its use for all KeyStone-I devices.  This is needed to allow an intial CVDD value of 1.1V.  It also has higher accuracy allowing use of lower precision resistors.

Tom