AM335x Spread Spectrum example request

Here is an example.  We are planning to add this in the next revision of the TRM.

SSC Configuration
The configuration of the spreading feature is not mandatory when programming the DPLL. This feature is
usually enabled when the DPLL clocks generate harmonics, which can potentially interfere with the GSM
carrier frequencies.
Once the clock generation control registers are configured, the spreading on the clock signal can be
configured as follows:
1. Calculate ModFreqDivider and DeltaMStep based on the desired peak-power reduction.
2. Configure the MODFREQDIV_EXPONENT, MODFREQDIV_MANTISSA, and DELTAMSTEP bit fields
according to the calculated values.
3. Enable the spreading using the DPLL_SSC_EN bit.

NOTE: Spreading on a clock must be carefully configured to avoid adding noise on frequencies that
are used by another module. For example, adding spreading on a clock to reduce noise on
GSM frequencies can move the generated noise to the frequency of the memory controller
and thus degrade its performance.

Example:
For fc = 160 MHz, Deviation = 1% peak from fc (Δf = 1.6 MHz) and fm = 16 kHz, the estimated peak power
reduction is 10 dB.
The output clock can be calculated using the following equation: fc= (finp × M)/((N + 1) × M2) (where M is a
software-controlled multiplier, N is a software-controlled divider, M2 is a software-controlled output divider,
fc stands for fCLKOUT_M2; for the calculation of other output clock frequencies and for more information, see ,
DPLLs Output Clocks Parameters, and the Clock Tree Tool).
The input clock is finp = 38.4 MHz. The following settings of the DPLL are required to have fc = 160 MHz: M
= 25, N = 2, M2 = 2. The value of M satisfies the restrictions: M – ΔM > = 20. Also, M + ΔM < = 2045.
fref can be calculated using the following equation:
fref = finp/(1 + N) = 12.8 MHz
ModFreqDivider can be calculated using the following equation:
ModFreqDivider = fref/(4 × fm) = 200
The exponent and mantissa of ModFreqDivider can now be calculated (where ModFreqDivider = Mantissa
× 2Exponent and it must be used as the minimal value for the exponent):
Mantissa = 100, Exponent = 1
Knowing the deviation and M, ΔM can now be calculated:
ΔM/M = 1% ≥ ΔM = 0.01 × 25 = 0.25
DeltaMStep can be calculated as follows:
DeltaMStep = ΔM/ModFreqDivider = 0.00125

The integer and fractional part of DeltaMStep can now be determined:
Integer part = 0, Fractional part = 0.00125 × 218 = 327 (for an 18-bit fractional part)
The DPLL can be configured as follows:
• MODFREQDIV_EXPONENT = 1
• MODFREQDIV_MANTISSA = 100
• DELTAMSTEP = 327

Regards,

James