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DM8148 modules Idle mode

Suresha N S
Expert 1070 points
Other Parts Discussed in Thread: SYSCONFIG

Hi all,

We are trying to reduce the power consumption by DM8148 in one of our designs.

We are executing following steps to put slave modules into idle mode . 

  • Write to <Module>_SYSCONFIG register's IDLEMODE bits to put module into Force-idle mode.
  • Write to CM_<Powerdomain>_<Module>_CLKCTRL[x] register's MODULEMODE bits to disable the specific module.
  • Read from CM_<Powerdomain>_<Module>_CLKCTRL[x] register's IDLEST bits to confirm the module status .

Even though read back value of IDLEST bits is 0x3 ( corresponding module is disabled ) , there is no change in the current consumption.

We have also observed one strange behavior.

With the same sequence mentioned above we put module into No-Idle mode. With this also after disabling the module from PRCM , read back status value is 0x3 (disabled). According to Section 2.1.2.2 Slave Idle Protocol of TRM , if we put the module into no-idle mode , writing to PRCM register to disable the module should not have any effect since PRCM will not get IdleAck from the Module.

We are not able to find out the reason behind this . Is there a problem with the sequence we are following ?


Regards,

Suresha.N.S.


  • 0
    Expert 1070 points

    Hi all,

    We have couple more queries regarding the power management .


    1. We are trying to operate DM8148 at 100 OPP . We have verified that all the core frequencies of the processors are compatible with 100 OPP as mentioned in table 7.4 of     datasheet . But if I try to reduce the core voltages to 1.1V the processor is hanging .  Below is the sequence we are following

    • Reduce the HDVICP core voltage (CVDD_HDVICP) to 1.1V - Wokring fine
    • Reduce  the DSP Core voltage  (CVDD_DSP) to 1.1V - Working fine
    • Reduce the ARM vcore Voltage (CVDD_ARM) to 1.1V - Working fine
    • Reduce the CORE voltage (VDD_CORE) to 1.1V - Processor Hangs

    Is the above sequence correct ? Are we Missing out something else ?



    2. In Our design we are not using some of the DM8148 cores like SGX,DSP . We tried to stop the core clocks by turning off the respective PLLs so as to reduce the power consumption . We programmed following registers to turn off the PLL.

    • SGXPLL_PWRCTRL - OFFMODE bit set to 1
    • SGXPLL_CLKCTRL - CLKOUTEN bit set to 0 

    Even after writing to this registers we observed from the sysfs entries that SGX_PLL clock is 20MHz. This suggests that the input clock to the SGX - PLL is given as the output .Is this correct ? Is there any other ways of completely powering off the PLLs ?

    Please post your suggestions.

    Regards,

    Suresha.N.S.