• State Resolved
  • Locked Locked
  • Replies 6 replies
  • Subscribers 99 subscribers
  • Views 479 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

VREF trace seperation

Kamesh Lakhwani
Prodigy 30 points
Other Parts Discussed in Thread: DM8107

Hi Feroz,

                Regarding the DDR3 interface with DM8107 processor, the trace width of VREF voltage is specified as 20 mils but the seperation is not recommended, what seperation is actually needed for VREF voltage to any other signals.

Regards

Kamesh Lakhwani

  • 0
    TI__Guru**** 393215 points
    Hi Kamesh,
     
    You can safely use the 4W rule from the net class guideline tables. For W=4mils this should give you 12mils gap. Of course, if it's possible to route VREF on a power/gnd plane layer it will be better.
  • 0 in reply to Biser Gatchev-XID
    Prodigy 30 points

    Thank you sir

    one more question,

    Clock Address Control Longest Manhattan distance i.e; CACLM = CACLMX + CACLMY + 300 mils.

    Also CK/Add_Cntrl nominal length = CACLM +/- 50 mils. But when practically routing or  trace matching on board trace length does  not exactly match CACLM as

    (i) CACLMX = Horizontal segment length/ Manhattan distance from Processor pin to DDR3 pin and

    (ii) CACLMY = Vertical segment length/ Manhattan distance from processor pin to DDR3 pin

    so how do we relate???

    Regards

    Kamesh Lakhwani

  • 0 in reply to Kamesh Lakhwani
    TI__Guru**** 393215 points
    Hi Kamesh,
     
    If I understood you correctly you ask how to match horisontal and vertical segments. You don't need to do this. The only requirement is that your total trace length is equal to CACLM +/- 50mils. If you work on Cadence Allegro, it has a set of nice report tools that can export to Excel both real trace length and Manhattan length for each net. Net Legth for pin to pin segments can also be exported.
  • 0 in reply to Biser Gatchev-XID
    Prodigy 30 points

    Hello sir,

                    As i told that practically it doesn't matches CACLM +/-50 mils as for trace matching we also sometime do serpentine routing depending upon the placement of memories and as per the board/space availability. what to do in such case?

    Regards

    Kamesh Lakhwani 

  • 0 in reply to Kamesh Lakhwani
    TI__Guru**** 393215 points
    I'm not sure I understand. If you can't meet the CACLM +/-50 mils requirement, you either have to try different placement of components or proceed at your own risk. TI doesn't support or assume responsibility if design guidelines are not followed by customer. As for serpentine routing, this is normal to use for trace length matching.
  • 0 in reply to Biser Gatchev-XID
    TI__Guru**** 393215 points
    By the way, can you tell me what is your CACLM and what is the real trace length?