Hi,
We are accessing DDR3 connected to FPGA through GPMC bus from DM8148. We are using address/data multiplexed mode. We are seeing an unexpected behaviour of gpmc_cs and gpmc_adv signals. I've attached the snapshot captured using Xilinx FPGA chipscope.
In the figure, following signals show the signaling issue.
i_gpmc_cs_n_IBUF à Chip select
i_gpmc_we_n_IBUF à Write Enable
i_gpmc_oe_n_IBUF à Output Enable
i_gpmc_addr_valid_n_IBUF à Address Data Valid
All the above signals are active low.
With the first two active chip select signals, there is no i_gpmc_we_n_IBUF or i_gpmc_oe_n_IBUF assertion. Hence there is no valid transaction which will lead to wastage of clock cycles.
Please let us know any possible causes for this behavior of GPMC.
