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unresolved issue with GMII to 88e6131

Other Parts Discussed in Thread: AM3874

I'm still battling trying to get the CPSW code to interface with the 88e6131. I have done everything suggested previously yet I'm still not able to get cpsw to talk over gmii to marvel switch. We're using EMAC[1] (only). I have done the following: 

  • made the changes to cpsw to allow only emac1, as described here: http://e2e.ti.com/support/dsp/davinci_digital_media_processors/f/716/p/211761/839179.aspx#839179 (thank you chaitanya godavarthi)
  • enabled the PLL path through PCIE and SATA. I can confirm that there's a 125Mhz clock coming out of the AM3874's GMII 
  • double and triple checked the PINCNTL register values 
  • the mdio bus is working and can see the 88e6131. My setup for the dsa device has dsa_chip_data.port_names { "port0", "port1", "port2", "cpu" }; Where port0 goes out to an RJ45 to the outside world. The DSA driver code sees the "phy"s on ports0 through port2, but obviously does not on "cpu". But it seems the CPSW code needs a phy to work correctly. During init, I can see that when the phy's are discovered, there are calls to get_phy_device and then phy_device_create on the 3 phy's that are discovered over mdio. The info on those phys are {{addr=0, phy_id=0x1410cb1, name="0:00:00"}, {addr=1, phy_id=0x1410cb1, name="0:00:01"}, {addr=2, phy_id=0x1410cb1, name="0:00:02"}}.  If in cpsw_slaves[0] (the only one) I set the .phy_id to "0:00:00"  it doesn't work either. I think that's the wrong approach anyhow as the cpsw should be talking to what "would be" phy "0:00:03" over gmii. 
  • the GMII_SEL register is clear
  • If i run "ifconfig -a" i see "eth0", "lo", "port0", "port1" and "port2".  If I manually "up" the eth0 interface, I can then "up" the portN interfaces as well. Once the portN's are up, I can see status messages when I plug and unplug cables into the ports. The steps are 1) `ifconfig eth0 10.20.0.31 up`  2) `route add default gw 10.20.0.2 eth0` 3) `ifconfig port0 up`.  If i try to "ping" something outside, I get a kernel dump that includes messages like "transmit queue timed out".. obviously because the cpsw code isn't aware there's something on the other end? because it didn't find a phy? 
I am not sure what to try next. My suspicion is that the CPSW code is in need of some major changes that, to be honest, are beyond what I can understand. 
  • Another thing worth mentioning is that we have put the 88e6131 in "test mode" .. which essentially means that all ports are enabled by default. We have confirmed that this works since we can connect a laptop to port2 of the switch and an ethernet connection to port1 or 0 and the switch does pass data through it, no problem. 

    On a side note.. it looks very much like "Brandon Reeves".. (a "TI Employee") was working on this very same thing, this past October. I asked what the outcome of the endeavor was, no reply. http://e2e.ti.com/support/dsp/davinci_digital_media_processors/f/716/t/220287.aspx    So what happened there? 

  • Hi Dennis,

        I m also working on ti81xx  (CPSW + Marvell switch 88E6085).
        My board configuration  :--    
                            EMAC 0 connects on PHY---> eth0
                            EMAC 1 Connects on Marvell switch --> eth1
        In kernel CONFIG_TI_CPSW_DUAL_EMAC option enabled .  

        1)  DSA device reg below    :-
             d->netdev = &ti814x_cpsw_device.dev

            DSA module probed but in dsa.c file net device found
            EMAC0 (eth0).
            dev = dev_to_net_device(pd->netdev);dev->name & dev->dev_addr print & check eth0 found.EMAC1 not found (eth1).

      2)  CPSW code strongly bound with phy_devices .
            How to break only EMAC1 from phy_devices  ??
       

    Thank You,
    Tejas.

  • Hi Tejas, 

    I'm still trying to get it working. Haven't had much luck.. 

    Dennis

  • Dennis

    CPSW driver doesn't have support for no phy mode. It can be done with minor changes to the driver. You can take davinci_emac driver as referrence in PSP kernel. In the mean time i will also post a patch implementing the same by next week.

    Regards
    Mugunthan  V N

  • Dennis

    I have implemented no phy mode for cpsw and i am attaching the patch and a sample patch how to modify the devices file to mad that slave to no phy mode.
    Note: This patch is only compile tested and not tested on any platform and this patch is applicable on ti81xx arago git repo master.

    Regards
    Mugunthan V N

    cpsw-no-phy-implementation.zip
  • Hi,

    EMAC 0---->[RGMII]--> connects on PHY-->KSZ9031 works fine

    EMAC 1 ----->[MII PHY Mode]---->Marvell switch detected. ifconfig -a  eth0,eth1,lan0,...all switch ports  detected only .(link not detected)

    1)Set phy_id = "0:10"  in cpsw_slave. bec switch addr 0x0A.phy_connect function failed PHY 10 not found . KSZ9031 PHY address detected & SW addr not detected ???

    Thank You,
    Tejas.