I am trying to write a EHCI driver for the omap 44430 using the Panda board. We are not using linux and other standard OS. We are using our own proprietary OS. I am trying to get the USB HOST port talk to the HUB and eventually setup the ethernet port on the Panda Board. I have enabled clock to the HSUSB module and set up the pin mux for the Port 1 as usbphy. Setup the AUX clock for the PHY. Initialized the the ehci registers and enabled the ehci interrupt.. After enabling the power to the HUB I get a Connect Status Change interrupt. The Port Reset bit in the PORTSC Set and Cleared after a delay. Now in the PORTSC the PED bit(Port Enabled/Disabled)is set. The Control QH is set up with QTDs and the QH address is set in the ASYNCLISTADDR register. But as soon as I set the ASE bit in the USBCMD register the ASYNCLISTADDR register contents change to 0x1E100C00. The USBSTS has the ASS bit and the REC bit set. But I do not get any interrupt. The QTDs are still active. What are the reasons for the ASYNCLISTADDR register to get corrupted on enabling the Async scheduling in the EHCI controller. I don't know If I have setup all the clocks correctly.
Here is a Dump of all the EHCI registers
{HCCAPBASE = 0x1000010, HCSPARAMS = 0x1313, HCCPARAMS = 0x20016, Resvered0 = 0x0, USBCMD = 0x80b29, USBSTS = 0xa008, USBINTR = 0x27,
FRINDEX = 0x18e, CTRLDSSEGMENT = 0x0, PERIODICLISTBASE = 0x81990000, ASYNCLISTADDR = 0x1e100c00, Resvered1 = {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
0x0, 0x0}, CONFIGFLAG = 0x1, PORTSC = {0x1007, 0x0 <repeats 14 times>}, INSNREG00 = 0x0, INSNREG01 = 0x200020, INSNREG02 = 0x80,
INSNREG03 = 0x1, INSNREG04 = 0x0, INSNREG05_ULPI = 0x0, INSNREG06 = 0x0, INSNREG07 = 0x0, INSNREG08 = 0x0}
Any help with this issue would be great.
Adding more info to my previous question.
The CM_L3INIT_CLKSTCTRL (0x4a009300) has a bit indicating the status of the Clock CLKACTIVITY_USB_DPLL_HS_CLK (bit 15). This bit is not set on my setup. Is this clock necessary for the EHCI controller to work? How can I enable this clock. Is there any document explaining how to enable this clock?