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Product Design Medha

Intellectual 430 points

I am working on TI C6678 processor. We developed a multi-core application with IPC Notify. The application worked well when we loaded the same code on all the processors and used the MultiProc module to prevent the execution of unwanted code from the slave processors. Now, we removed all unwanted code from the slave processors and loaded different programs in the L2SRAM(with Reserved memory excluded) of each slave core. Also we added extra tasks and HWI in the master processor This resulted in the following problems

The processors were not synchronizing with IPC_start and with the setting SYNCALL. This worked previously when there is same code in all the processors. The problem is not repeatable, some times it is working.
Most of the times(usually when the program is restarted from CCS Debug)setting break points has no effect. The break points are ignored yet they are shown as enabled in CCS.

Any ideas on what could have gone wrong?

Regards

Srikanth

over 12 years ago

0 Robert Tivy over 12 years ago

TI__Mastermind 18260 points

Hi Srikanth,

Whenever a problem report mentions "sometimes" and "most of the time" I'm inclined to suspect subtle cache issues.

For your issue #2 with CCS breakpoints, CCS writes a special opcode in place of the program's normal instruction at the BP location (for SW breakpoints, which is the default type; a HW breakpoint is different and doesn't overwrite the instruction). I wonder if that BP opcode is either:
a) written to L2SRAM while the real instruction resides in L1P cache, thus resulting in the CPU executing the real instruction from cache and not seeing the BP, or
b) written to cache but then invalidated before the CPU encounters that instruction.

Can you try using HW breakpoints instead? If they work more reliably then that would point us in a certain direction for further investigation.

For your issue #1 with lack of Ipc_start sync, I wonder about the cacheability of Shared Region #0, where all the sync activity takes place. Have you set the "cacheEnable" property of SR #0 to "true" in your application .cfg file? If so, you don't want cache enabled for SR #0, it should be set "false".

Related to the SR cache setting (which really just instructs the Ipc code to perform cache maintenence, or not) have you set any MAR bits to enable cacheing of certain memory areas?

You also mention that you added tasks and HWI to the master application. From where are you calling Ipc_start() on the master and the slave apps? How do the new master application tasks relate to the other tasks on that processor?

Finally, it's usually helpful to open up ROV (for each processor) and look around to see if any system or task stack has overflowed, or any other general badness. Check that each task in the system is listed properly and has good values.

Feel free to post application source files and .cfg files and I can poke around.

Regards,

- Rob