• State
  • Locked Locked
  • Replies 2 replies
  • Subscribers 99 subscribers
  • Views 649 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

PCIe stuck in link training c6678

dongcheng chen
Prodigy 10 points

I try to build a two line link per PCIe v1.1 between c6678 DSP and Virtex 6 FPGA. The DSP works as RC and the FPGA as EP. But I don't get the link up at the initialization of PCIe.,the DSP PCIe is now stuck in LTSSM state 0x02 POLL_ACTIVE.What may cause POLL_ACTIVE?

  • 0
    TI__Genius 12065 points

    Could you check if the PLL clock has been locked on FPGA side please?

    There is one similar issue in the following thread due to the PLL unlock on FPGA. 

    http://e2e.ti.com/support/dsp/c6000_multi-core_dsps/f/639/t/218446.aspx

    Please check the following items as the other member mentioned:

    If the PLL don't lock control

    • if you used DC coupling capacitors an the clock lines.

    • the voltage level on the clock line.

    • Control the input jitter, it should be less than 300 ppm

  • 0
    Intellectual 460 points
    Hello, During my tests with C6657 as RC and some commercial PCIe cards I found two things that can cause link init to fail: - Clock frequency must be accurate enough (within the 300ppm as already mentioned). I used a separate PCIe clock generator. - Some chipset didn't like DC coupling. The EVM is configured for EP mode, having coupling capacitors only on one direction's signal pair. When using it as RC, the other direction's signal pair should also have capacitors. best regards Guenter