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EtherCAT with DDR3?

Other Parts Discussed in Thread: AM3358, TLK110

Hi,

We are debugging AM3358 EtherCAT board.

Problem: IN port seems to be working but OUT port is not working.

I already read this forum aout OUT port issue, and applied recent firmware 1.0.0.6.

But the result is same.

Our design is little different from ICE board.

Some pins are remaped, about TLK110's we changed only the reset pin of the OUT port.

And we use DDR3 DRAM not like DDR2 of ICE board.

I know only the PRU control the phy chips wholly, and CPU does not concerned.

Is it correct?

Is the PRU can control the reset pin also, and can be used with DDR3?

Is there any timing issue on PRU if we use DDR3?

So some EtherCAT function could be spoiled?

I guess it may not be a problem because IN port works well.

But I need your confirmation.

And I read PG1.0 has silicon bug concerned about OUT port function.

What means PG?

We have the chip marking

AM3358ZCZD72

2AACY2W GI

962 ZCZ

Is PG2.0 and has no probem about OUT port?

Thanks.

Regards.

  • Hi,

    TLK110 reset is done by A8 application and not PRU firmware -(see sdk\platform\am335x\src\am335x_indcomm_startup.c - init_tlk function). You need to adapt this to match the GPIO used for reset of port1 and configure pinmux for that GPIO correctly in sdk\protocols\ethercat_slave\ecat_appl\EcatStack\ecat_appl_cnfg.h

    Yes - EtherCAT firmware does not access DDR3. So no dependency there.

  • HI,

    can you clarify what you mean with OUT port not working?

    We only have an issue with EtherCAT redundancy mode and AM335x PG1.0. Normal chained EtherCAT operation with all silicon is supported as long as the master is on the side of the IN port. PG2.0 also supports redundancy mode (master connection switches to OUT port if there is a line break on IN side). Now we just released rev E of the datasheet on the web. According to section 6.1 all PG2.0 devices are marked with an 'A' device revision right after the device number. So it seems you do not have the latest PG and therefor you may experience issues when connecting a master to the OUT port.

    Regards.

  • Hi PratheeshGangadhar,

    It's my mistake. The software engineer told me that CPU handle the reset pin.

    And thanks for confirmation about DDR3 usage.

    Regards.

  • Hi Frank Walzer.

    We connected two slave like this:

    master(PC TwinCAT) -- slave1 IN --slave1 OUT -- slave2 IN

    The TwinCAT always detect only the first slave.

    But the OUT port still send some EtherCAT packet if we connect it to other PC's ethernet port.

    Because, we can see packets in WinPCAP software.

    Each slave works fine if only one slave is connected to the master.

    master -- ICE board -- our slave: (works fine)

    master -- our slave -- ICE board: (ICE board not works)

    It seems like we have old silicon chips.

    Then, you mean the OUT port of PG1.0 must work well if second slave connected, and not a master.

    Regards.

  • HI,

    do you have one or two TI boards (ICE or IDK) that are known to work in this configuration?

    I see two possibilities for your issues:

    - Twincat often closes Port B (OUT) of a device if the next one in the chain is not immediately found. This requires to manually enable Port B of your slave1.

    - The change in Reset of TLK110 for OUT port could cause the TLK110 to not startup correctly. There are several reset requirements (e.g. clock needs to be stable). You might have to check your schematics again. Make sure there is no conflict between AM335x Sysboot pins and the TLK110 PU/PDs that drive default phy configuration.

    Regards.

  • Hi,

    We have many ICE boards. They are working fine in this configuration.

    Thank you for your kind suggestions.

    We will check that.

    Regards.