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Single PHY interface for AM3352

Jamie Maxwell
Expert 1530 points
Other Parts Discussed in Thread: AM3352

We are doing an AM3352 design and have a couple of options for PHY devices. One is an MII device and one is RGMII. Board is designed for both but only one will be populated.

Since we have two different Phys and use MII or RGMII interfaces, the question is if we need two software loads, or will kernel auto probe (via MDIO) for connected Ethernet transceiver?

Thanks

J

  • 0
    TI__Intellectual 2750 points

    Jmax

    From driver side, there is no change when CPSW is connected to MII or RGMII phy. You need to take care of pin-mux whether to configure MII or RGMII. For example you can refer "arch/arm/mach-omap2/board-am335xevm.c" in PSP release where Beagle bone is configured to MII and EVM is configured to RGMII by checking the board revision.

    So if you have a board revision logic you can achieve what you are looking for.

    Regards
    Mugunthan V N

  • 0 in reply to Mugunthan V N
    TI__Guru 62945 points

    Please read Advisory 1.0.16 in the AM335x Silicon Errata.

    An external low jitter 50 MHz RMII clock source is required if the RMII PHY is not able to source the RMII clock to AM335x.

    Regards,
    Paul