On a C5535, is it necessary to clear all bits in IFR0 and IFR1 prior to executing the IDLE instruction assuming global interrupts (INTM) are enabled? Does it matter or not if the interreupts flagged in IFR0/IFR1 are enabled in IER0/IER1?
The following wiki artical suggest we have to clear them ...
Make sure that no interrupts are pending in IFR0/IFR1 when you try to idle the CPU. You can clear pending interrupts by writing 0xFFFF to IFR0/IFR1.
Step 4 in the IDLE2 procedure in section 1.5.6.1 of the TRM says to clear IFR0 and IFR1. However step 5 then says to enable the appropriate wakeup interrupts in IER0 and IER1 which also means to disable the others. It seems to gaurantee no flags are pending then you should disable enable bits in IER before clearing pending flags in IFR. Almost as if steps 4 and 5 are reversed. Is the goal really to gaurantee no flags are pending in IFR before executing IDLE?
My question is, what happens if we execute IDLE while bits are set in either IFR0 or IFR1? Will IDLE immediately exit?
