Other Parts Discussed in Thread: SYSCONFIG
Hi, we have to use pandaboard (OMAP4460) for driving LCD with MIPI DSI Interface (Video mode). Using Linaro's kernel.
We got the error message when boooting on --> "omapdss DSI error: failed to set complexio power state to 1"
We do not know how to fit it. Is it caused by the wrong setting of DSI_COMPLEXIO_CFG1? Thanks for your suggestion!
The parameter were listed below:
LCD's resolution: 540 * 960,
Pixel Clock: 154MHz
Our setting as:
struct omap_dss_device omap4_panda_lcd_device = {
.name = "lcd",
.driver_name = "panel-dsi",
.type = OMAP_DISPLAY_TYPE_DSI,
.data = &panel_dsi_data,
.phy.dsi = {
.clk_lane = 3,
.clk_pol = 0,
.data1_lane = 1,
.data1_pol = 0,
.data2_lane = 2,
.data2_pol = 0,
.type = OMAP_DSS_DSI_TYPE_VIDEO_MODE,
},
.clocks = {
.dispc = {
.channel = { .lck_div = 1, // LCD
.pck_div = 5, // PCD
.lcd_clk_src = OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC,
},
.dispc_fclk_src = OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC,
},
.dsi = {
.regn = 16, // DSI_PLL_REGN
.regm = 180, // DSI_PLL_REGM
.regm_dispc = 5, // PLL_CLK1 (M4)
.regm_dsi = 5, // PLL_CLK2 (M5)
.lp_clk_div = 10, // LPDIV
.dsi_fclk_src = OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI,
},
},
.channel = OMAP_DSS_CHANNEL_LCD, };
static struct omap_video_timings panel_dsi_timings = {
.x_res = 540,
.y_res = 960,
.pixel_clock = 154000, //80842,
.hfp = 62,
.hsw = 4,
.hbp = 154,
.vfp = 84,
.vsw = 1,
.vbp = 15,
};
static const struct omap_dss_dsi_videomode_data vm_data = {
.hsa = 1,
.hfp = 115,
.hbp = 47,
.vsa = 1,
.vfp = 84,
.vbp = 15,
.vp_de_pol = true,
.vp_vsync_pol = true,
.vp_hsync_pol = false,
.vp_hsync_end = false,
.vp_vsync_end = false,
.window_sync = 4,
};
THANKS
root@android:/ # cat /d/omapdss/dsi1_regs
DSI_REVISION 00000030
DSI_SYSCONFIG 00000015
DSI_SYSSTATUS 00000001
DSI_IRQSTATUS 00000180
DSI_IRQENABLE 0015c000
DSI_CTRL 00000100
DSI_COMPLEXIO_CFG1 48000213
DSI_COMPLEXIO_IRQ_STATUS 00000000
DSI_COMPLEXIO_IRQ_ENABLE 3ff07fff
DSI_CLK_CTRL 00044001
DSI_TIMING1 7fff7fff
DSI_TIMING2 7fff7fff
DSI_VM_TIMING1 00000000
DSI_VM_TIMING2 00000000
DSI_VM_TIMING3 00000000
DSI_CLK_TIMING 00000101
DSI_TX_FIFO_VC_SIZE 00000000
DSI_RX_FIFO_VC_SIZE 00000000
DSI_COMPLEXIO_CFG2 00000000
DSI_RX_FIFO_VC_FULLNESS 00000000
DSI_VM_TIMING4 00000000
DSI_TX_FIFO_VC_EMPTINESS 00000000
DSI_VM_TIMING5 00000000
DSI_VM_TIMING6 00000000
DSI_VM_TIMING7 00000000
DSI_STOPCLK_TIMING 00000080
DSI_VC_CTRL(0) 00000000
DSI_VC_TE(0) 00000000
DSI_VC_LONG_PACKET_HEADER(0) 00000000
DSI_VC_LONG_PACKET_PAYLOAD(0) 00000000
DSI_VC_SHORT_PACKET_HEADER(0) 00000000
DSI_VC_IRQSTATUS(0) 00000000
DSI_VC_IRQENABLE(0) 000000db
DSI_VC_CTRL(1) 00000000
DSI_VC_TE(1) 00000000
DSI_VC_LONG_PACKET_HEADER(1) 00000000
DSI_VC_LONG_PACKET_PAYLOAD(1) 00000000
DSI_VC_SHORT_PACKET_HEADER(1) 00000000
DSI_VC_IRQSTATUS(1) 00000000
DSI_VC_IRQENABLE(1) 000000db
DSI_VC_CTRL(2) 00000000
DSI_VC_TE(2) 00000000
DSI_VC_LONG_PACKET_HEADER(2) 00000000
DSI_VC_LONG_PACKET_PAYLOAD(2) 00000000
DSI_VC_SHORT_PACKET_HEADER(2) 00000000
DSI_VC_IRQSTATUS(2) 00000000
DSI_VC_IRQENABLE(2) 000000db
DSI_VC_CTRL(3) 00000000
DSI_VC_TE(3) 00000000
DSI_VC_LONG_PACKET_HEADER(3) 00000000
DSI_VC_LONG_PACKET_PAYLOAD(3) 00000000
DSI_VC_SHORT_PACKET_HEADER(3) 00000000
DSI_VC_IRQSTATUS(3) 00000000
DSI_VC_IRQENABLE(3) 000000db
DSI_DSIPHY_CFG0 1e481d3a
DSI_DSIPHY_CFG1 420a1a6a
DSI_DSIPHY_CFG2 b800001a
DSI_DSIPHY_CFG5 60000000
DSI_PLL_CONTROL 00000000
DSI_PLL_STATUS 000001c9
DSI_PLL_GO 00000000
DSI_PLL_CONFIGURATION1 1081681f
DSI_PLL_CONFIGURATION2 00656008
root@android:/ # cat /d/omapdss/dispc_irq
period 572101 ms
irqs 0
FRAMEDONE 0
VSYNC 0
EVSYNC_EVEN 0
EVSYNC_ODD 0
ACBIAS_COUNT_STAT 0
PROG_LINE_NUM 0
GFX_FIFO_UNDERFLOW 0
GFX_END_WIN 0
PAL_GAMMA_MASK 0
OCP_ERR 0
VID1_FIFO_UNDERFLOW 0
VID1_END_WIN 0
VID2_FIFO_UNDERFLOW 0
VID2_END_WIN 0
VID3_FIFO_UNDERFLOW 0
VID3_END_WIN 0
SYNC_LOST 0
SYNC_LOST_DIGIT 0
WAKEUP 0
FRAMEDONE2 0
VSYNC2 0
ACBIAS_COUNT_STAT2 0
SYNC_LOST2 0
THANKS.... Best Regard, Owen
