• State
  • Locked Locked
  • Replies 7 replies
  • Subscribers 98 subscribers
  • Views 360 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

RSZ_INT_EOF0 interrupt is not received

Lajos Rancz
Expert 1065 points

Hi all,

We are developing a camera application based on DM8148. The software is own, it is not IPNC RDK based. We have the following configuration:

  • Sensor pixel clock is 95.833 MHz
  • Sensor native resolution is 1936 x 1296 pixels
  • RZA_V_DIF and RZA_H_DIF is 256 (no down/upscale, just YUV conversion)
  • RZB_V_DIF and RZB_H_DIF is 3*256 (640x360 YUV output)
  • DMA_RZA/DMA_RZB is 0, so the bandwidth limiter is turned off
Usually the received interrupts sequence is REG, EOF1, LAST_PX, EOF0; REG, EOF1, LAST_PX, EOF0; REG, EOF1, LAST_PX, EOF0 and so on. 
But sometimes the EOF0 interrupt is missing. What could be the problem? It is normal?
Regards,
Lajos 
  • 0
    Expert 1065 points

    Additional information:

    • the sensor type is Aptina MT9P031
    • the sensor is connected via Parallel Interface
    And a question: should the BTE context be in continuous mode?

    Regards,
    Lajos 
  • 0 in reply to Lajos Rancz
    Expert 1065 points

    If I understand correctly, the BTE is transparent when the rotating is turned off. So, it should not be a problem.

    Regards,
    Lajos 

  • 0
    Expert 1065 points

    Hi,

    I've checked, and the RSZ_FIFO_IN_BLK_ERR and RSZ_FIFO_OVF interrupts are not asserted, so the RSZ doesn't report any error. By the way, when the RSZ_INT_EOF0 is missing, then the RSZ_INT_DMA is also.

    Regards,
    Lajos 

  • 0 in reply to Lajos Rancz
    Expert 1065 points

    Regarding the ISS manual:

    "This event signals that the minimum vertical blanking period has not been respected causing errors in the input data buffering submodule. This event will be triggered when the rsz_int_reg event of frame N is triggered before the rsz_int_dma of frame N + 1. This event would typically happen at the transition between two frames because there is not enough vertical blanking between frames: the firmware must take care to ensure enough vertical blanking. 
    The hardware cannot recover from this error. It will be required to perform a reset of the IP."

    In our case the hardware continuous to operate normally, but the RSZ_INT_REG event is triggered before RSZ_INT_DMA. So what is this???

    Regards,
    Lajos

     

  • 0 in reply to Lajos Rancz
    TI__Expert 8780 points

    Lajos,

    Can you check if VDINT0 is triggered for each captured frame?

    Typically you can configure VDINT0 to be (height-5) line number and the interrupt should get triggered whenever the corresponding line is captured by ISIF module. If ISIF VDINT0 is stable and continuous for you then the problem could be in IPIPE/RSZ configuration.

    Regards

    Rajat

  • 0 in reply to Rajat Sagar
    Expert 1065 points

    Hi Rajat,

    Thanks for the reply. I think the VDINT0 is triggered for each captured frame because the RSZ_INT_REG is triggered for each captured frame. Only thre ResizerA (native resolution, YUV422 => YUV420SP) and the RSZ_INT_DMA IRQs are missing.

    Regards,
    Lajos