Hi,
I would like to know the detailed information of AM5K2E04/02.
Please see the below.
1) L1 cache : How many words of one line for L1 cache?
2) L1 cache : Could L1 cache use as a SRAM memory? Then, is address of L1 cache locked?
3) L2 cache : How many words of one line for L2 cache?
4) L2 cache : Could L2 cache use as a SRAM memory? Then, is address of L2 cache locked?
5) L3 memory : What is protocol for L3 memory? Is it MOESI? Then, is it 64byte cache line?
6) How is latency of memory L1, L2 and L3? Is L2 19clk?
7) Internal bus spec: Is the speed of TeraNet CPU/3 clk? The bus width are three types 256, 128, 32 bit? And speed are 2Tbps, 50GBaud? Is MSM connected by 256bit bus?
8) Cache coherency : Is cache coherency kept between L1D, L2, MSM and DDR?
9) How is pay load size? 128Bytes?
10) How is power consumption? Is typ. 6W@2Core? Also Can user power down A15 core separately?
11) What is the package of AM5K2E04/02?
I appreciate your quick reply. I must the above spec to our customer on this Friday.
Best regards,
Michi
