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uart+edma on c6748

izzet ozcelik
Intellectual 585 points

Hi

I am using uart on c6748. I want to received data from the PC via uart1 and transfer the data to the C6748 memory via EDMA.

The edma will work in ping pong buffering set up and interrupt the pc once the data has been received.

I have been using uart on its own succefully. I am using edma with McBSP in a ping-pong sturcture succesfully.

But I could not get uart+edma pingpong  structure working.

I can receive data correctly from UART1 with polling the uart LSR . There is no problem there.

WHen I run the code edma seems to be doing nothing.

I do not see any Event Register set.

The below is the configuring of UART.

Any comment is appreciated.

Best regards

izzet

 

 

 //Reset (disable) transmitter and receiver  

CSL_FINST(ISPUartRegs->PWREMU_MGMT, UART_PWREMU_MGMT_UTRST, RESET);  

CSL_FINST(ISPUartRegs->PWREMU_MGMT, UART_PWREMU_MGMT_URRST, RESET);

 

 //////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////        

// Set communication speed  

// Enable access to DLL and DLH  

CSL_FINST(ISPUartRegs->LCR, UART_LCR_DLAB, ENABLE);  

CSL_FINS(ISPUartRegs->DLL,  UART_DLL_DLL, BAUD115200_16xOverSampling_C6748_L);  

CSL_FINS(ISPUartRegs->DLH,  UART_DLH_DLH, BAUD115200_16xOverSampling_C6748_H);  

CSL_FINST(ISPUartRegs->LCR, UART_LCR_DLAB, DISABLE);

 //////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////

// Disable all interrupts  

// enable access to IER  

CSL_FINST(ISPUartRegs->LCR,  UART_LCR_DLAB,  DISABLE);

//CSL_FINS(DispLayUartRegs->LCR, UART_LCR_DLAB,  0x0);  

// disable all interrupts  

ISPUartRegs->IER = (Uint32)0x00000000; 

 

 //////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////  

// FCR  

// Enable fifos and reset them; IIR is at the same address as FCR

 // FIFOEN must be set to 1 before other FCR registers are written  

CSL_FINST(ISPUartRegs->FCR, UART_FCR_FIFOEN,   ENABLE);  

CSL_FINST(ISPUartRegs->FCR, UART_FCR_RXFIFTL,  CHAR14);       

//Enable DMA mode for the UART to generate data receive events to the EDMA  

CSL_FINST(ISPUartRegs->FCR, UART_FCR_DMAMODE1, ENABLE);

 CSL_FINST(ISPUartRegs->FCR, UART_FCR_TXCLR,    CLR);

 CSL_FINST(ISPUartRegs->FCR, UART_FCR_RXCLR,    CLR);  

CSL_FINST(ISPUartRegs->FCR, UART_FCR_FIFOEN,   ENABLE);  

 //////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////  

//line control register; format of data  

CSL_FINST(ISPUartRegs->LCR, UART_LCR_BC,   DISABLE);  

CSL_FINST(ISPUartRegs->LCR, UART_LCR_SP,   DISABLE);  

CSL_FINST(ISPUartRegs->LCR, UART_LCR_EPS,  ODD);  

CSL_FINST(ISPUartRegs->LCR, UART_LCR_PEN,  DISABLE);  

CSL_FINST(ISPUartRegs->LCR, UART_LCR_STB,  1BIT);  

CSL_FINST(ISPUartRegs->LCR, UART_LCR_WLS,  8BITS);  

CSL_FINST(ISPUartRegs->LCR, UART_LCR_DLAB, DISABLE);  

 //////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////

 //////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////  

//modem control register  

// Disable auto RTS & CTS Flow control; loopback mode is disabled  

CSL_FINST(ISPUartRegs->MCR, UART_MCR_AFE,   DISABLE);  

CSL_FINST(ISPUartRegs->MCR, UART_MCR_LOOP,  DISABLE);  

CSL_FINST(ISPUartRegs->MCR, UART_MCR_OUT2,  DISABLE);  

CSL_FINST(ISPUartRegs->MCR, UART_MCR_OUT1,  DISABLE);  

CSL_FINST(ISPUartRegs->MCR, UART_MCR_RTS,   DISABLE);  

CSL_FINST(ISPUartRegs->MCR, UART_MCR_DTR,   DISABLE);  

//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////

 

 

 //////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////        

// select oversampling ratio;  CSL_FINST(ISPUartRegs->MDR, UART_MDR_OSM_SEL, 16XOVERSAMPLING);  //////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////

 

 

 

 

 

 

 ////////////////////////////////////////////////////////////////////////////////////////////////////////////////////  

// Start UART  

CSL_FINST(DispLayUartRegs->PWREMU_MGMT, UART_PWREMU_MGMT_FREE,   RUN);  

CSL_FINST(ISPUartRegs->PWREMU_MGMT, UART_PWREMU_MGMT_URRST,  ENABLE);  

CSL_FINST(ISPUartRegs->PWREMU_MGMT, UART_PWREMU_MGMT_UTRST,  ENABLE);  

////////////////////////////////////////////////////////////////////////////////////////////////////////////////////

  • 0
    TI__Guru* 84110 points

    Izzet,

    For debugging purposes, do not enable the DMA EER bit for this UART event in the EDMA3 register set. This will prevent the DMA channel from running, but you will see the ER register bit set if the event is getting from the UART to the EDMA3 module. This is a first starting point to determine if the problem is on the UART side or the EDMA3 side.

    Regards,
    RandyP

  • 0 in reply to RandyP
    Intellectual 585 points

    Hi Randy

     

    I do that by not enabling any Event Enable Registers. I see two sets of region registers. Shadow region 0 and shadow region 1.

    DSP is accesing the edma3 via shadow region 1. ER is  equal to 0x00000000. I do not get this. The uart setup is easy.

    I only need FIFO enabled and DMA mode enables on FCR of uart1 which i assume I did.

    How can I view FCR of the UART. It is only write only.

     

    Since the start of this work, I never seen ER being set. So this must mean UART1 receive events are not getting through.

     

     

     

     

    Best regards

    izzet

  • 0 in reply to izzet ozcelik
    TI__Guru* 84110 points

    Izzet,

    It is good to know which side of this line to look. Thank you for reporting the status that ER=0 when EER=0.

    Although I am criticizing the TI examples somewhat, I do not like the use of the CSL_FINST macro for a write-only register. I would go so far as to say that it is incorrect to use this macro for any write-only register, especially when specific bits must be used in a certain way and their values must be maintained. The W1C fields do not matter so much, but the DMAMODE1 field is critical and should not be used this way, in my opinion.

    Instead, start with a temp variable

    example said:

    unsigned in value=0;

    and use CSL_FINST to build the value to be written to FCR

    example said:

    // FCR   

    // Enable fifos and reset them; IIR is at the same address as FCR

    value = 0;   // FIFOEN must be set to 1 before other FCR registers are written   

    CSL_FINST(value, UART_FCR_FIFOEN,   ENABLE); 

    ISPUartRegs->FCR = value;  

    CSL_FINST(value, UART_FCR_RXFIFTL,  CHAR14);         //Enable DMA mode for the UART to generate data receive events to the EDMA   

    CSL_FINST(value, UART_FCR_DMAMODE1, ENABLE);  

    CSL_FINST(value, UART_FCR_TXCLR,    CLR);  

    CSL_FINST(value, UART_FCR_RXCLR,    CLR);   

    CSL_FINST(value, UART_FCR_FIFOEN,   ENABLE);   

    ISPUartRegs->FCR = value;

    For testing purposes, it may help to set the RXFIFTL value to CHAR1.

    The IIR.FIFOEN field can be read and will let you know if the FIFO is enabled by your writes to the FCR.

    Regards,
    RandyP