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C6657 Keystone device

Michi Yama
Guru 10030 points
Other Parts Discussed in Thread: TMS320C6657

Hi,

I would like to know the feature of C6657.

Now our customer is evaluating Keystone device (C6657) performance. I need the information for the below.

* Arithmetic calcuration :  32MACS/Core/cycle,  seven stage pipeline --- are these data right?

* L1 cache :  Can the address on L1cache be locked?

* L2 cache :  Can the address on L2 cache be locked? 

* Memory latency :  How many clock  for each cache?   L1P: 3(1) clk, L1D:3(1)clk, L2:4(2) clk,   Core Access Time : 1 cycle ,   Are these data right?  Then, how about L3?

 * Cache coherency :  L1P : No,  L1D: HW support,  L2: HW support,  external memory : No,   Are these data right?

I appreciate quick reply.

Best regards,

Michi

                                   

 

  • 0
    TI__Mastermind 30825 points

    This information is documented in the User Guide's and Data Manual's that are available on the product page --> TMS320C6657

    The Arithmetic Calculation and most cache details can be found in the Data Manual.

    Further details on the cache are documented in the 'C66x DSP Cache User Guide'. 

    Best Regards,

    Chad