Hi,
First, I created this post just not to mess with this one (http://e2e.ti.com/support/dsp/c6000_multi-core_dsps/f/639/t/242344.aspx).
Sometimes we get Instruction Fetch Exceptions and the registers content are printed, so we can see them and debug the application. In the post I mentioned, Chad says that B15 register indicates where the error is(in that case it's in Local L2 memory space) and also that B3 indicates where it branched from. I've also seen in the forum (link) that the NRP register contains " the address at which the invalid opcode was fetched", so my question is: is there a manual where the function of these registers are described?
Thanks
