C66x memory read performance

Single is one memory access from the Cache Line that is accessed.  Burst, is for more than one memory access from the Cache Line that's accessed.  Note that as the cache line is filled in, that the later accesses actually become cache hits.

Hi Chad,

OK, so it's mean that the first byte will take Single Read cycles and the next reads will take the Burst Read Cycles, is that correct? why should the Victim Burst Read takes more time than the Victim Single Read? as the cache line is read on the first miss,

Thanks,

HR

For the first access of the burst it will take the single access time.  But the Burst speed is an average. For example, for the L1D miss of an L2 access, the first and 2nd access, take 7 cycles giving a 3.5 cycle average, by the 3rd access the cache line should be in place.

Best Regards,

Chad

Hi Chad,

OK, but for local L2 miss it takes for single read 7 cycles which is for the first read and than the next one takes 3.5 cycles (No victim) and 10 cycles (victim) the 3.5 cycles is making sense as it is the second byte to read but than why in the case of Victim the second byte to read is bigger (10) than the first byte to read (7),

Thanks,

HR