aintc module access from a9 4430/60

The term AINTC is used in AM35xx/OMAP-L13x and other TI''s processors, for these one reference link is

http://processors.wiki.ti.com/index.php/Configuring_GPIO_Interrupts.

In OMAP you can find this information in chapters "4 Dual Cortex-A9 MPU Subsystem" and "17 Interrupt Controllers" (see 17.4.1) for OMAP4430/OMAP4460 TRM (Technical Reference Manual) that can be downloaded from User's Guide section in

http://www.ti.com/product/omap4430

Hi Manuel

I see this information but I don't see details of registers, how to use the interrupt controller.

I look to linux source code , the interrupt module is almost the same like interrupt controller from AM335x(seeing the structure of registers), for this reason I copied the driver from AM335x to omap4 but if I don't know the registry structure of interrupt module and details about these registers I can not create a driver for this module, without this module I cannot use almost all interfaces, like DISPC, MMC/SD etc, the same problem I have with the PL310 cache controller and the MMU for the A9 cores, no details, the TRM is direct me to infocenter.arm.com/help/index.jsp but on this site i find only general information, nothing useful to create a driver.

If I look on linux source code for these information I think that I finish every driver in about one year. And this is not good for a developer.

I work to a sdk for omap4 like StarterWare to create standalone applications, for now I created the GPIO, UART and I2C drivers and apy's, but here I stuck because I need a interrupt driver, and a DMA driver.

Best regards.

Yes, I just reviewed what you mentioned, and all the information related is redirected to ARM site.

PL310 information

infocenter.arm.com/help/topic/com.arm.doc.ddi0246b/DDI0246B_l2cc_pl310_r1p0_trm.pdf

Cortex A9 Interrupt

I couldn't find a pdf for this documentation.

infocenter.arm.com/help/topic/com.arm.doc.ddi0388-/

I am not sure if adding direct links could affect, I don't know if the spider or web search engines could be affected, if that is the case please mention it in order to remove the links and just mention the filenames, I am not sure if there is some agreement to read the files I just search for them in general search.

There is only one reference to "Table 17-2 shows the Cortex-A9 MPU INTC interrupt mapping." that I thought was the register information.

Thank you very much, in "DDI0246B_l2cc_pl310_r1p0_trm.pdf" is explained everything about PL310 controller.

Now I have another problem.

The PL310 has some registers that can be write in secure mode.

About this I understand that the MPU to be able to modify secured registers, is necessary to put the MPU in secure mode.

In debug mode I look to base address if is correct and the base address of PL3310 is correct, I can see all data inside PL310 registers.

After calling a function to modify a secured register i put the controller in secure mode but the controller go to "Data abort" when the MPU try to write in a secured register from PL310.

this is an example:

    asm("    MSR   cpsr_c, #0x13|0xC0");


    pl310->pl310_clean_inv_way = 0xFFFF;//Non secured register
    pl310->pl310_intr_clear = 0xFFFF;//Non secured register
    pl310->pl310_ctrl |= pl310_ctrl_cache_enable;//Secured register
    CPUSwitchToUserMode();

When try to write to "pl310->pl310_ctrl" go to "Data abort".

Best regards.

Ok, thank you wery wery much :)