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DM8148: HDMIPLL_FRACDIV register's FRACTIONALM field format

Atsushi Narita
Prodigy 30 points

Hi.

I have a question about HDMIPLL_FRACDIV register's FRACTIONALM field format on DM8148.

For example, Fractional M is 0.5

In the case,

  FRACTIONALM field should set  0x00005 ?

    otherwise,

  FRACTIONALM field should set  0x20000 (Fixed-point) ?


Regards.

  • 0
    TI__Genius 11470 points

    Hello,

    Please, post what software package you are using? Thank you.

    BR

    Vladimir

  • 0 in reply to Vladimir-XID
    Prodigy 30 points

    Hi, Vladimir

    I'm using ezsdk_dm814x-evm_5_05_02_00 package on DM8148EVM.
    And RDK 3.3.0 package on DM8127.

    I'd like to change a hdmi pixel clock from 148.5MHz(60Hz) to 148.351648MHz(59.94Hz).

    Therefore, I want to set a value of 'Fractional M' to HDMIPLL_FRACDIV Register.

    But I don't know about Format of HDMIPLL_FRACDIV[17:0] :(

    Regards,


  • 0 in reply to Atsushi Narita
    TI__Mastermind 43875 points

    You should be able to change the pixel clock frequency through sysfs entries and IOCTLs. Check the HDVPSS documentation that should be included with the RDK.

    In short though, you need to look for the "timings" sysfs entry.

    e.g.

    echo 148500,1920/88/148/44,1080/4/36/5,1 > /sys/devices/platform/vpss/display0/timings
where:
148500: display pixel clock(KHz)
1920: display width
88: horizontal front porch
148: horizontal back porch
44: horizontal sync width
1080: display height
4: vertical front porch
36: vertical back porch
5: vertical sync width
1: progressive output

    You should also be able to directly change the pixel clock frequency in the driver by adding a new enumerated mode.

    I am not 100% sure what files need modified but posting the the Linux/PSP forums should get you an answer fairly quick.

    BR,

    Steve

  • 0 in reply to Steve Clynes
    TI__Genius 11470 points

    Hello,

    Thanks a lot, Steve.

    BR

    Vladimir

  • 0 in reply to Steve Clynes
    TI__Guru**** 476695 points

    Hi,

     

    It is not set on Linux/A8, pixel clock is set on M3/Bios driver.

     

    Rgds,

    Brijesh

  • 0 in reply to Brijesh Jadav
    Prodigy 30 points

    Hi,

    I temporarily modified following RDK source code for changing hdmi pixel clock 148.351648MHz.

      ~/yourapp/Source/ti_tools/ipnc_psp_04_04_00_01/kernel/drivers/video/ti81xx/vpss/system.c

      /*program the PLL with desired divider*/

      static int system_platformpllcfg(u32 base, u32 n, u32 m, u32 f, u32 m2, u32 sd, u32 clkctrl)
      {

      #if 1
        __raw_writel( (f & 0x0003FFFF) | \
                                 ((sd & 0xFF) << 24), (base + FRACDIV) );
      #else

       __raw_writel(((__raw_readl(base + FRACDIV)) & 0xFFFFFF) | \

                                 ((sd & 0xff) << 24), (base + FRACDIV));
      #endif

    }

    Then, I use following HDMI_PLL coefficient values, and evaluated it.

        n = 19, m = 1483, f = 51648, m2 = 10, sd = 6

    As a result, it synchronized at 59.94Hz.

    Regards,

  • 0 in reply to Atsushi Narita
    TI__Genius 11470 points

    Hi Atsushi,

    I am glad to hear that the issue is solved. Thank you very much for the feedback.

    BR

    Vladimir