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uPP Port

Tony Flynn
Intellectual 270 points

Hi There

I want to know if it is possible to reset the uPP port FIFO after initialising the port.  I have written my own drivers for this port and have them working almost as I want.  I notice that anytime I initialise or reset the uPP port and then populate the DMA Descriptor registers the uPP port seems to fill my buffer with old junk from the uPP FIFO buffers.  This only seems to happen after a init or reset of the uPP port.

Is there a way to reset the uPP FIFO / Descriptors?  Currently after a reset I populate the DMA registers and ignore the trash it returns before I repopulate them to catch my real data.

All help appreciated

Thanks


Tony

  • 0
    TI__Guru* 84110 points

    Tony,

    Which device are you using?

    The uPP User's Guide for that device will have all available information on its use, but there may be subtle differences from one to the next.

    Regards,
    RandyP

  • 0 in reply to RandyP
    Intellectual 270 points

    Hi Randy

    Part is C6748.  The user guide doesn't really cover much about the uPP FIFO/DMA.  There is a uPP reset procedure but it doesn't seem to reset the FIFO. 

    "Software reset clears the uPP internal state machines but does not reset the contents of the uPP
    registers. The following procedure performs a software reset on the uPP peripheral."

  • 0 in reply to Tony Flynn
    Intellectual 270 points

    Something I also notice is that when I load my DMA descriptors and receive data over the uPP port to my designated buffer it works great, I can repeat this all day long and I get my data back to my buffer.  Is soon as I read a byte of data in that buffer and then loop around to refill my buffer it skips filling a chunk of 64 bytes in the location of where I read my data. but populates all the other locations correctly.  If I read all my data from the buffer, ie, say copy the buffer completely then on the next loop no data will enter the buffer

    Why does reading my data buffer screw things up for the next run? And how do I avoid this?

    Thanks


    Tony

  • 0 in reply to Tony Flynn
    TI__Guru* 84110 points

    Tony,

    Have you tried the Power and Sleep Controller (PSC) to apply a module reset to the uPP? The PSC is described a little in the datasheet, and then detailed more in the System Reference Guide.

    Can you example your buffers in a Memory Browser in CCS? From your latest post, my first thought is that you have a cache coherency issue. If so, you can tell by the colors in the Memory Browser window whether the data is cached or not, and you can click off the cache view to see the data stored at the memory location instead of the cache.

    You can turn off caching by clearing the associated MAR bits for your buffers.

    A better choice (in many cases) is to use the cache invalidate commands after the DSP is finished reading from a buffer and before the DSP tries to read from that buffer again.

    Regards,
    RandyP

  • 0 in reply to RandyP
    Intellectual 270 points

    Hi Randy

    This response looks like you have me looking in the right place.  I did tackle the PSC registers to power cycle the uPP port but I still have these random issues which seem to be more memory based issues.  I am looking into your second suggestion now.  In the memory browser I can see that the first 48 bytes of my 1500 word buffer are grey indicating L1D cache, the remaining data of my array buffer is white, this presumably means the data is being read from the actual memory location.

    When I click off the L1D cache I see the missing 48 bytes of by buffer test pattern as I want them to be...Excellent!  No I am at the point as to why this is happening and how do I stop it.

    I see the MAR registers mentioned in the C6748 datasheet, where would I find info on the cache invalidate commands?

    Many thanks again for solving this one for me.

    Tony 

  • 0 in reply to Tony Flynn
    TI__Guru* 84110 points

    Tony,

    The two documentation places to look are the datasheet and the Megamodule Reference Guide.

    In the Training section of TI.com, there is a training video set for the C6474. It may be helpful for you to review the first three modules. In particular, the Memory & Cache Module may help you understand some of the cache features and options available. You can find the complete video set here.

    There may be some more specific training material for the C6748, such as the "C6000 Embedded Design Workshop Using BIOS" training course. You can find materials from it on the TI Wiki Pages, and you might consider signing up for a live class if one would be available nearby when you need it. You can look around TI.com for other online training material, too.

    Regards,
    RandyP

  • 0 in reply to RandyP
    TI__Guru* 84110 points

    Tony,

    Also, BIOS has cache coherency commands available, too. The BIOS documentation, and maybe CCS Help searches, would be a good place to find these.

    Understanding which operations you want to run, and when, is what you will get from the training materials, especially the Memory & Cache video I mentioned. And there is usually a good module on Cache in the Workshops like the one I mentioned above, too.

    Regards,
    RandyP