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C6678 HCSL clock termination

fearghal rudden
Intellectual 480 points
Other Parts Discussed in Thread: CDCM6208
Hi,
I have posted on the Clocks & Timers section of the e2e forum about termination of HCSL clock signals to the C6678 and the issue was solved but I have further questions if you can explain this to me?
Here is my original post:
http://e2e.ti.com/support/clocks/f/48/t/240818.aspx
The question I still have is related to the reason to terminate the HCSL clock signals with a resistor tied to ground as stated in the above post. I had previously browsed the DSP forums and found information indicating that HCSL signals should only require AC termination similar to LVDS signals which have only an AC terminating capacitor in series with the line close to the receiving pin on the DSP.
I removed the capacitor and have now only placed a 50 ohm terminating resistor to ground on the HCSL clock pins. My DSP is up and running. Can you confirm the termination required and why my DSP now operates with a terminating resistor to ground and with no AC termination capacitor?
Thank you,
Best Regards,
Fearghal 

  • 0
    TI__Mastermind 42545 points

    Hi Fearghal,

    The guidence given to us is that the LJCB in the C6678 is self-biasing and must be driven by an AC terminated clock. The 50ohm resistors to ground on the driver side of the AC capacitors are a requirement for the clock driver.  Since HCSL is only used as a clock by the PCIE backplane I'm assuming that the resistors would be on the far end of the clock line where the driver was impliemented.  Why are you implementing an HCSL clock driver with the CDCM6208 for the C6678?

    Regards, Bill

  • 0 in reply to Bill Taboada
    Intellectual 480 points

    Hi Bill,

    The CDCM6208 could provide the required clocks I needed in pin mode. It was a requirement for my design to operate without the need to communicate the clock generator. The CDCM6208 had only one setting that could provide the necessary clocks and they are as follows:

    Y0: 100MHz (LVPECL)

    Y1: 100MHz (LVPECL)

    Y2: 250MHz (LVPECL)

    Y3: 250MHz (LVPECL)

    Y4: 100MHz (HCSL)

    Y5: 100MHz (HCSL)

    Y6: 125MHz (HCSL)

    Y7: 66.67MHz (HCSL)


    Since I knew that HCSL signals were not a problem for the C6678, I proceeded with the above part in pin mode.

    It was not initially obvious to me that the termination recommended in the CDCM6208 datasheet was for the driver, I had presumed it was the recommended termination for a receiver. I have terminated the HCSL signals through 50 ohm to GND (without the AC coupling capacitors) close to the receiver pins. As I mentioned, I can see the clocks running and my board and the DSP seem to be operating without any issues. I will implement the AC coupling when revising the design, unless you think I should include them on my development boards now? Could it cause any issues?

    Thanks Bill,

    Regards, Fearghal

  • 0 in reply to fearghal rudden
    TI__Mastermind 42545 points

    Hi Fearghal,

    I'll make a note to add a caution about extra components that might be needed by the driver, especially for HCSL.  I've been looking over the pin select settings for the CDCM6208 and I can see why you chose the selection that you did.  There may be some possibilities that use LVDS but I'll have to do some research.  Do you mind if I ask how you have clocks Y0-Y7 connected to C6678?

    Regards, Bill

  • 0 in reply to Bill Taboada
    Intellectual 480 points

    Hi Bill,

    I initially connected the clocks directly from the CDCM6208 to the C6678 through 100nF series capacitors. I have since removed the series capacitors on the HCSL lines and just added a 50ohm termination to GND on each of these HCSL lines. All of the signal terminations are placed close to the C6678 pins.

    Thanks again,

    Rgds,

    Fearghal

  • 0 in reply to fearghal rudden
    TI__Mastermind 42545 points

    Hi Fearghal,

    I'm sorry but my question wasn't clear.  Could you tell me which of the clock outputs from the CDCM6207 are connected to which of the clock inputs of the C6678?  It's clear that none of the pin selectable configurations are ideal for the C6678 and I wanted to know how you had used the particular configuration that you chose to implement your design.

    Regards, Bill

  • 0 in reply to Bill Taboada
    Intellectual 480 points

    Sorry Bill,

    They are connected as follows:

    Y0: 100MHz (LVPECL) PCIECLK_P/N

    Y1: 100MHz (LVPECL) PASSCLK_P/N

    Y2: 250MHz (LVPECL) SRIOSGMIICLK_P/N

    Y3: 250MHz (LVPECL) N/C

    Y4: 100MHz (HCSL) CORECLK_P/N

    Y5: 100MHz (HCSL) N/C

    Y6: 125MHz (HCSL) N/C

    Y7: 66.67MHz (HCSL) DDRCLK_P/N

    Regards,

    Fearghal