• State Resolved
  • Locked Locked
  • Replies 1 reply
  • Subscribers 98 subscribers
  • Views 611 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

c6748 L2 rams

izzet ozcelik
Intellectual 585 points

 

Hi

I am looking at the memory map of c6748. There are 2 L2 ram blocks of size 256kBytes.

DSPL2RAM    o = 0x00800000  l = 0x00040000 /* 256kB L2 Internal RAM */

    SHDSPL2RAM  o = 0x11800000  l = 0x00040000 /* 256kB L2 Shared Internal RAM */

    SHRAM       o = 0x80000000  l = 0x00020000 /* 128kB Shared RAM */

 

There is also the shared ram of size 128. In total 640kBytes of ram other than L1 rams. This is a lot of memory...

Are these all the same in terms of speed and usability.

Can I use all these 3 blocks as I wish. I know that edma requires the memory that would be involved in dma operations to be in shared ram.

Other than thath is there any intricate features of these and the way they should be used.

I want to use DSPL2RAM  only for one purpose in my application. Basically to load a temporary data. My code and other arrays would be SHDSPL2RAM  .

 

 

Best regards.

 

izzet

 

 

  • 0
    TI__Guru* 84110 points

    Izzet,

    What you are looking at is an excerpt from a linker .cmd file for aiding the linking process. The datasheet is where you can look to find out how many memories there are and how big they are.

    The DSP L2 RAM is 256KB in size. This single memory module resides at two memory ranges, starting at 0x00800000 and at 0x11800000. DSP code can run at addresses in the 0x00800000 range and can access data variables in the 0x00800000 range, and can also access the same memory locations in the 0x11800000 range. Other bus masters, like the EDMA3 modules, can only access the DSP L2 RAM memory from the global address range starting at 0x11800000. The memory ranges starting at 0x00800000 and 0x11800000 are the same physical memory; if you write 0xa5a5a5a5 to 0x00800000 using DSP code, you can then read 0xa5a5a5a5 at address 0x11800000 using the DSP or EDMA3.

    There is an additional 128KB RAM at 0x80000000. The DSP and all bus masters may access this additional Shared RAM starting at address 0x80000000.

    I am not sure where in the C6748 documentation this is explained.

    Regards,
    RandyP