OMAP-L138 Timer register read latency

Maxime Renaudet

Hi everyone,

I've been running into a problem lately, I try to time stamp some events the most precisely possible.

The first thing I notice is that from the time a pulse is generated on a gpio and the time the first instruction is exexuted in a FIQ is 550ns which is quite big already.
Then, I read a timer counter, which take 210 nano seconds (63 cycles, I hope I'm mistaken) on tmr64P2, it's even longer if I try to read tmr64P0.

It becomes more disturbing when you try to date an event relatively to an other.

Is it normal delays, or am I missing something. Knowing that all my FIQ is in cache and locked in cache. All this is run by ARM core.

Thanks,

Maxime

over 12 years ago

0 Hyun Kim over 12 years ago

TI__Genius 14965 points

Hi,

What is a frequency of ARM core? And what software (OS) is running?

Regards,

Hyun

0 Maxime Renaudet over 12 years ago in reply to Hyun Kim

Intellectual 510 points

Hi,

ARM runs at 300Mhz, a home made OS is running on it, the FIQs are never disabled.

Regards,

Maxime

0 Renjith Thomas over 12 years ago in reply to Maxime Renaudet

Guru 31670 points

Maxime,

Have you enabled I-cache? Also how about d-cache?

Also how are you measuring the latency?

0 Maxime Renaudet over 12 years ago in reply to Renjith Thomas

Intellectual 510 points

Well, I Cache & D cache are enabled, data & instructions are locked in cache.

To measure the latency I set a GPIO high at the beginning of the FIQ isr and set it back low at the end of it. If I only write NOPs, the FIQ execution time is really the number of NOPs multiplied by 3.3333ns (which is normal since it runs at 300Mhz.). I read this GPIO with an oscilloscope.

As soon as I add : "LBBO R0, tmrAddr, 4", it adds 200ns to the FIQ execution time, I managed to reduce to 400ns, so 50% of this time is due to reading a timer ...

0 Renjith Thomas over 12 years ago in reply to Maxime Renaudet

Guru 31670 points

Maxime,

Have you factored the time required to toggle the GPIOs?

0 Maxime Renaudet over 12 years ago in reply to Renjith Thomas

Intellectual 510 points

Yes I did try to toggle the GPIO multiple times, the swtich is really fast.

0 Renjith Thomas over 12 years ago in reply to Maxime Renaudet

Guru 31670 points

Maxime,

Do you have the numbers for GPIO toggling? Have you taken care of these numbers while calculating the timer latencies?

0 Maxime Renaudet over 12 years ago in reply to Renjith Thomas

Intellectual 510 points

Alright, the code I execute is pretty simple,

STR 1, gpioAddr

LDR r0, tmrAddr

STR 0, gpioAddr

So, I don't really have to take into account the time to toggle the GPIOs, do I ? I read the pin state with an oscilloscope, I assume the time to switch from high to low is the same as low to high.

Thanks for your answers

0 Renjith Thomas over 12 years ago in reply to Maxime Renaudet

Guru 31670 points

Maxime,

Since load and store instructions are dependent on the memory/bus access times, each load store can take different amount of time. For e.g, a read from internal SRAM can happen in 4 cycles and from a GPIO controller register in 10 cycles or more. Since Timer and GPIO controller registers are part of the same bus, you'll be able to see same/different time in accessing these registers.

So it will be better to monitor the time for each GPIO toggling, as I have see close to 150ns time in doing just GPIO toggle in DM8148 platform.

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OMAP-L138 Timer register read latency