Using the TI AM335x Arm processor:
Require to interface from an FPGA to the GPMC interface. Desire to provide a single write cycle, single read cycle, burst read cycle, burst write cycle.
Question:
From the software user side, is there a command for a single write cycle on the GPMC interface, another command for a single read cycle on the GPMC interface, another command for a burst write cycle on the GPMC interface, another command for a burst read cycle interface.
The single write or read cycles interfaces to registers in the FPGA. The burst write cycle is to interface to a fifo (single address, data out are multiple bytes). The burst read cycle is to interface to a fifo (single address, data in are multiple bytes).
