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TMS320C67xx EMIFB to SDRAM interface

Conrad Seymour
Prodigy 40 points

We are using a Micron MT48LC2M32B2P-6 64M (512K x 32 x 4 BANKS) SDRAM on the EMIFB interface; this SDRAM is capable of 167MHz.  We are presently running this part at 150 MHz and are only using this external SDRAM for initialization.  Our question is two part.  1)  Is there a maximum speed for the EMIFB interface?  This part is 32 bit wide and we only have one SDRAM on the PCB.  2) Also, we are concerned that the 150 MHz clock runs continuously and we would like to turn off the clock after initialization is complete (especially because of premature aging on the present rev of this DSP). 

  • 0
    TI__Mastermind 21285 points

    Hi Conrad,

    150MHz is a bit high for the EMIFB.  It is limited to 133MHz.  From the DS;

     

  • 0 in reply to Michael S
    TI__Mastermind 21285 points

    Regarding decreasing the EMIF CLK, there should be no negative repercussions other than slower memory transactions.  Strictly speaking, since your reducing the number of logic state switches in a specified amount of time within the device by reducing the operating speed, this should lead to longer device life but considering how long device life is rated for even at maximum operation, I do not believe that there would be a noticeable difference but I would recommend consulting Micron.   I can say for certain that keeping access even across the rows will increase life expectancy.

    Let me look into suspending the SDRAM during operation past initialization.  My concern is that the EMIFB occupies the entire 0xCxxx xxxx memory range (256MB) and I believe that it would take modification of the linker configuration to prevent your application from accessing it.  I'll look into this and get back with you.

     

    EDIT: As you indicated in your original post, decreasing the clock rate would lead to increase longevity. 

    My previous information was provided solely from the perspective of the life of the actual memory device and did not take into account the current C6747 silicon errata which clearly states that operation at lower clock rates lead to increased lifespan.

    Thank you Randy