EDMA manually-triggered transfer fail sometimes

Qiu Hong

Hi,

My chip is belong to C67x.
I use EDMA to transfer data between on-chip memory and off-chip memory with manually-trig.
I use EDMA3 LLD to operate the EDMA. I register a callback function for EDMA completion.
For debug , the EDMA use early completion mode.

The work flow is as below.
Every time cpu trig the EDMA to transfer data, pint the information, then cpu wait 12 seconds.
If EDMA complete a data transfer, some information will be printed by the callback function.
Then next data transfer will do as before.
I find cpu trig 100 EDMA data transfer, but only finish 80 data transfer.

Only the manually-triggered EDMA use queue 2. The cpu read the EMR\EMRH\CCERR registers after cpu wait 12 seconds and these registers's value is all zeros. So manually-triggered EDMA do not miss, but why EDMA data transfer don't finish?

The regitser reading method is as below.
#define EDMA_CC_BASE (0X9000000)
#define EDMA_EMR (volatile int *)(EDMA_CC_BASE+0x300))
DBGprintf(msg,"DMA reg2:=%x,%x",(*(EDMA_EMR)),(*(EDMA_CCERR)));
The DBGprintf of my will print information on serial port.

Then I find ARM also use EDMA, ARM ues 4 channel and mapping to queue 0 which have the highest priority.
I cann't close or change ARM 's EDMA setting directly.But I try to close the EDMA channels used by ARM in DSP before my manually-trig.
By this way, the EDMA channels used by ARM are partly closed. And I find my manually-trig change to seldom fail.
Can EDMA used by ARM have so big affect on my manually-trig?
I catch watermark of queue 0, it's value is one.
I can not make sure if EDMA channels used by ARM affect my manually-triggered EDMA. Can anyone help me?

over 12 years ago

0 RandyP over 12 years ago

TI__Guru* 84110 points

Qiu Hong,

Thank you for reformatting your post. The other one will be removed as redundant.

Please state which DSP chip you are using. C67x is not enough to be certain how to help you. I do not think of a C67x device that has an ARM, so this is confusing. We need to establish more information.

Do the data transfers occur and only the callback fails to execute?

Are you using an EVM or known development board, or is this on your custom board?

Do you the failures when the ARM is not running at all?

Regards,
RandyP

0 Qiu Hong over 12 years ago in reply to RandyP

Prodigy 100 points

Hi, RandyP

Thank you for your reply.
The DSP chip I am using is belong to TMS320DR6xx(Automotive Media Applications Processors).
I am using the custom board.

I just do a test, I init src data as 0x1111 and dst data as 0xaaaa. DMA transfer data from src to dst.
When callback function is called,I find the dst data is still oxaaaa.
This is strange.

I can not close or change DMA channels used by ARM directly, because another workmates are responsible the code of ARM.
They may not want to change the DMA setting code.
I try to close DMA channels used by ARM by set EECR and QEECR registers.(ARM use 2 DMA event channels and 2 QDMA channels)
This method cann't close ARM's DMA completely. But from the num of callback success, it still show Obviously difference.
When ARM's DMA is closed by this method, callback can fail one time for several thousand times.

Best Regards

Hong

0 RandyP over 12 years ago in reply to Qiu Hong

TI__Guru* 84110 points

Hong,

Thank you for using the Answered button. The Answered flag has been removed since your question has not been resolved. When you are completely satisfied, please mark the appropriate post with Answered for our benefit and for future readers.

If you have an FAE assigned to support your company for this product, please contact them and make them aware of this E2E thread. You will get the best support with the most people aware of your issue. I do not have detailed access to information on the TMS320DR6xx processors, and these are generally not supported on the E2E forum for that reason. I will try to assist you with generic questions or information, and hopefully we can reach a solution with you.

In most of our ARM+DSP devices, there is an EDMA3 Shadow Region that is dedicated to the ARM (usually Shadow Region 0) and to the DSP (usually Shadow Region 1). Please tell me what the values are in the DRAE0 and DRAE1 registers?

Can you provide a dump of all of the EDMA3 registers in hex format? The best format may be to use a struct overlay like the CSL_Edma3ccRegsOvly and capture a set of screen shots from a CCS Expressions window.

This will help to understand more about what you are doing. I would like to understand which channels are being used by the ARM & DSP and their configurations. The PARAM for those channels is important, too.

A possible cause for the symptoms you have described is cache coherency. In the Training section of TI.com, there is a training video set for the C6474. It may be helpful for you to review several of the modules that apply to C64x+ items, even though the C6474 is a different device yet has (three of) the same DSP core. In particular, the Memory & Cache Module and the EDMA3/QDMA/IDMA Module may help you understand some of the features and options available within the cache and EDMA3 portions of the common architectures of the two devices. You can find this complete video set here.

The C64x+ Megamodule Reference Guide would also be a good document to review. It will include some good textual descriptions of the architecture and registers for handling cache coherency issues.

Regards,
RandyP

0 Qiu Hong over 12 years ago in reply to RandyP

Prodigy 100 points

Hi, RandyP

I will have a holiday from 09 Feb to 16 Feb for Chinese New Year.

I will provide dump of EDMA3 registers to you after 16 Feb.

Thank you for your help.

Best Regards

Hong

0 RandyP over 12 years ago in reply to Qiu Hong

TI__Guru* 84110 points

Hong,

Happy New Year! Have a safe and pleasant holiday.

Regards,
RandyP

0 Qiu Hong over 12 years ago in reply to RandyP

Prodigy 100 points

Hi, RandyP

1. EDMA'S registers dump is as below:

EDMA REGS:name=PID,addr=9000000,value=40014c00
EDMA REGS:name=CCCFG,addr=9000004,value=3335445
EDMA REGS:name=QCHMAP[0],addr=9000200,value=0
EDMA REGS:name=QCHMAP[1],addr=9000204,value=0
EDMA REGS:name=QCHMAP[2],addr=9000208,value=0
EDMA REGS:name=QCHMAP[3],addr=900020c,value=0
EDMA REGS:name=QCHMAP[4],addr=9000210,value=0
EDMA REGS:name=QCHMAP[5],addr=9000214,value=0
EDMA REGS:name=QCHMAP[6],addr=9000218,value=381c
EDMA REGS:name=QCHMAP[7],addr=900021c,value=3c1c
EDMA REGS:name=DMAQNUM[0],addr=9000240,value=0
EDMA REGS:name=DMAQNUM[1],addr=9000244,value=30333
EDMA REGS:name=DMAQNUM[2],addr=9000248,value=0
EDMA REGS:name=DMAQNUM[3],addr=900024c,value=0
EDMA REGS:name=DMAQNUM[4],addr=9000250,value=0
EDMA REGS:name=DMAQNUM[5],addr=9000254,value=0
EDMA REGS:name=DMAQNUM[6],addr=9000258,value=33
EDMA REGS:name=DMAQNUM[7],addr=900025c,value=0
EDMA REGS:name=QDMAQNUM,addr=9000260,value=0
EDMA REGS:name=QUEPRI,addr=9000284,value=213
EDMA REGS:name=EMR,addr=9000300,value=100000
EDMA REGS:name=EMRH,addr=9000304,value=0
EDMA REGS:name=EMCR,addr=9000308,value=0
EDMA REGS:name=EMCRH,addr=900030c,value=0
EDMA REGS:name=QEMR,addr=9000310,value=0
EDMA REGS:name=QEMCR,addr=9000314,value=0
EDMA REGS:name=CCERR,addr=9000318,value=0
EDMA REGS:name=CCERRCLR,addr=900031c,value=0
EDMA REGS:name=EEVAL,addr=9000320,value=0
EDMA REGS:name=DRA[0].DRAE,addr=9000340,value=ffffc0ff
EDMA REGS:name=DRA[0].DRAEH,addr=9000344,value=3cfcffff
EDMA REGS:name=DRA[1].DRAE,addr=9000348,value=170c
EDMA REGS:name=DRA[1].DRAEH,addr=900034c,value=30000
EDMA REGS:name=DRA[2].DRAE,addr=9000350,value=0
EDMA REGS:name=DRA[2].DRAEH,addr=9000354,value=0
EDMA REGS:name=DRA[3].DRAE,addr=9000358,value=0
EDMA REGS:name=DRA[3].DRAEH,addr=900035c,value=0
EDMA REGS:name=DRA[4].DRAE,addr=9000360,value=0
EDMA REGS:name=DRA[4].DRAEH,addr=9000364,value=0
EDMA REGS:name=DRA[5].DRAE,addr=9000368,value=0
EDMA REGS:name=DRA[5].DRAEH,addr=900036c,value=0
EDMA REGS:name=DRA[6].DRAE,addr=9000370,value=0
EDMA REGS:name=DRA[6].DRAEH,addr=9000374,value=0
EDMA REGS:name=DRA[7].DRAE,addr=9000378,value=0
EDMA REGS:name=DRA[7].DRAEH,addr=900037c,value=0
EDMA REGS:name=QRAE[0],addr=9000380,value=ff
EDMA REGS:name=QRAE[1],addr=9000384,value=0
EDMA REGS:name=QRAE[2],addr=9000388,value=0
EDMA REGS:name=QRAE[3],addr=900038c,value=0
EDMA REGS:name=QRAE[4],addr=9000390,value=0
EDMA REGS:name=QRAE[5],addr=9000394,value=0
EDMA REGS:name=QRAE[6],addr=9000398,value=0
EDMA REGS:name=QRAE[7],addr=900039c,value=0
EDMA REGS:name=QUEEVTENTRY[0].QUEEVT[0],addr=9000400,value=c7
EDMA REGS:name=QUEEVTENTRY[0].QUEEVT[1],addr=9000404,value=15
EDMA REGS:name=QUEEVTENTRY[0].QUEEVT[2],addr=9000408,value=15
EDMA REGS:name=QUEEVTENTRY[0].QUEEVT[3],addr=900040c,value=15
EDMA REGS:name=QUEEVTENTRY[0].QUEEVT[4],addr=9000410,value=c7
EDMA REGS:name=QUEEVTENTRY[0].QUEEVT[5],addr=9000414,value=15
EDMA REGS:name=QUEEVTENTRY[0].QUEEVT[6],addr=9000418,value=15
EDMA REGS:name=QUEEVTENTRY[0].QUEEVT[7],addr=900041c,value=15
EDMA REGS:name=QUEEVTENTRY[0].QUEEVT[8],addr=9000420,value=15
EDMA REGS:name=QUEEVTENTRY[0].QUEEVT[9],addr=9000424,value=15
EDMA REGS:name=QUEEVTENTRY[0].QUEEVT[10],addr=9000428,value=15
EDMA REGS:name=QUEEVTENTRY[0].QUEEVT[11],addr=900042c,value=c7
EDMA REGS:name=QUEEVTENTRY[0].QUEEVT[12],addr=9000430,value=15
EDMA REGS:name=QUEEVTENTRY[0].QUEEVT[13],addr=9000434,value=c7
EDMA REGS:name=QUEEVTENTRY[0].QUEEVT[14],addr=9000438,value=c7
EDMA REGS:name=QUEEVTENTRY[0].QUEEVT[15],addr=900043c,value=c7
EDMA REGS:name=QUEEVTENTRY[1].QUEEVT[0],addr=9000440,value=9b
EDMA REGS:name=QUEEVTENTRY[1].QUEEVT[1],addr=9000444,value=dc
EDMA REGS:name=QUEEVTENTRY[1].QUEEVT[2],addr=9000448,value=f7
EDMA REGS:name=QUEEVTENTRY[1].QUEEVT[3],addr=900044c,value=67
EDMA REGS:name=QUEEVTENTRY[1].QUEEVT[4],addr=9000450,value=ca
EDMA REGS:name=QUEEVTENTRY[1].QUEEVT[5],addr=9000454,value=da
EDMA REGS:name=QUEEVTENTRY[1].QUEEVT[6],addr=9000458,value=11
EDMA REGS:name=QUEEVTENTRY[1].QUEEVT[7],addr=900045c,value=7c
EDMA REGS:name=QUEEVTENTRY[1].QUEEVT[8],addr=9000460,value=d6
EDMA REGS:name=QUEEVTENTRY[1].QUEEVT[9],addr=9000464,value=ed
EDMA REGS:name=QUEEVTENTRY[1].QUEEVT[10],addr=9000468,value=2a
EDMA REGS:name=QUEEVTENTRY[1].QUEEVT[11],addr=900046c,value=a4
EDMA REGS:name=QUEEVTENTRY[1].QUEEVT[12],addr=9000470,value=d1
EDMA REGS:name=QUEEVTENTRY[1].QUEEVT[13],addr=9000474,value=f5
EDMA REGS:name=QUEEVTENTRY[1].QUEEVT[14],addr=9000478,value=9b
EDMA REGS:name=QUEEVTENTRY[1].QUEEVT[15],addr=900047c,value=d4
EDMA REGS:name=QUEEVTENTRY[2].QUEEVT[0],addr=9000480,value=41
EDMA REGS:name=QUEEVTENTRY[2].QUEEVT[1],addr=9000484,value=12
EDMA REGS:name=QUEEVTENTRY[2].QUEEVT[2],addr=9000488,value=b
EDMA REGS:name=QUEEVTENTRY[2].QUEEVT[3],addr=900048c,value=92
EDMA REGS:name=QUEEVTENTRY[2].QUEEVT[4],addr=9000490,value=d7
EDMA REGS:name=QUEEVTENTRY[2].QUEEVT[5],addr=9000494,value=c6
EDMA REGS:name=QUEEVTENTRY[2].QUEEVT[6],addr=9000498,value=78
EDMA REGS:name=QUEEVTENTRY[2].QUEEVT[7],addr=900049c,value=a3
EDMA REGS:name=QUEEVTENTRY[2].QUEEVT[8],addr=90004a0,value=9e
EDMA REGS:name=QUEEVTENTRY[2].QUEEVT[9],addr=90004a4,value=53
EDMA REGS:name=QUEEVTENTRY[2].QUEEVT[10],addr=90004a8,value=b7
EDMA REGS:name=QUEEVTENTRY[2].QUEEVT[11],addr=90004ac,value=6b
EDMA REGS:name=QUEEVTENTRY[2].QUEEVT[12],addr=90004b0,value=e0
EDMA REGS:name=QUEEVTENTRY[2].QUEEVT[13],addr=90004b4,value=70
EDMA REGS:name=QUEEVTENTRY[2].QUEEVT[14],addr=90004b8,value=e5
EDMA REGS:name=QUEEVTENTRY[2].QUEEVT[15],addr=90004bc,value=fa
EDMA REGS:name=QUEEVTENTRY[3].QUEEVT[0],addr=90004c0,value=8
EDMA REGS:name=QUEEVTENTRY[3].QUEEVT[1],addr=90004c4,value=8
EDMA REGS:name=QUEEVTENTRY[3].QUEEVT[2],addr=90004c8,value=8
EDMA REGS:name=QUEEVTENTRY[3].QUEEVT[3],addr=90004cc,value=8
EDMA REGS:name=QUEEVTENTRY[3].QUEEVT[4],addr=90004d0,value=8
EDMA REGS:name=QUEEVTENTRY[3].QUEEVT[5],addr=90004d4,value=9
EDMA REGS:name=QUEEVTENTRY[3].QUEEVT[6],addr=90004d8,value=9
EDMA REGS:name=QUEEVTENTRY[3].QUEEVT[7],addr=90004dc,value=8
EDMA REGS:name=QUEEVTENTRY[3].QUEEVT[8],addr=90004e0,value=8
EDMA REGS:name=QUEEVTENTRY[3].QUEEVT[9],addr=90004e4,value=9
EDMA REGS:name=QUEEVTENTRY[3].QUEEVT[10],addr=90004e8,value=8
EDMA REGS:name=QUEEVTENTRY[3].QUEEVT[11],addr=90004ec,value=8
EDMA REGS:name=QUEEVTENTRY[3].QUEEVT[12],addr=90004f0,value=8
EDMA REGS:name=QUEEVTENTRY[3].QUEEVT[13],addr=90004f4,value=8
EDMA REGS:name=QUEEVTENTRY[3].QUEEVT[14],addr=90004f8,value=8
EDMA REGS:name=QUEEVTENTRY[3].QUEEVT[15],addr=90004fc,value=8
EDMA REGS:name=QSTAT[0],addr=9000600,value=10000
EDMA REGS:name=QSTAT[1],addr=9000604,value=0
EDMA REGS:name=QSTAT[2],addr=9000608,value=0
EDMA REGS:name=QSTAT[3],addr=900060c,value=10003
EDMA REGS:name=QWMTHRA,addr=9000620,value=10101010
EDMA REGS:name=QWMTHRB,addr=9000624,value=0
EDMA REGS:name=CCSTAT,addr=9000640,value=0
EDMA REGS:name=AETCTL,addr=9000700,value=0
EDMA REGS:name=AETSTAT,addr=9000704,value=0
EDMA REGS:name=AETCMD,addr=9000708,value=0
EDMA REGS:name=MPFAR,addr=9000800,value=0
EDMA REGS:name=MPFSR,addr=9000804,value=0
EDMA REGS:name=MPFCR,addr=9000808,value=0
EDMA REGS:name=MPPA,addr=900080c,value=fef6
EDMA REGS:name=ER,addr=9001000,value=0
EDMA REGS:name=ERH,addr=9001004,value=0
EDMA REGS:name=ECR,addr=9001008,value=0
EDMA REGS:name=ECRH,addr=900100c,value=0
EDMA REGS:name=ESR,addr=9001010,value=0
EDMA REGS:name=ESRH,addr=9001014,value=0
EDMA REGS:name=CER,addr=9001018,value=0
EDMA REGS:name=CERH,addr=900101c,value=0
EDMA REGS:name=EER,addr=9001020,value=301700
EDMA REGS:name=EERH,addr=9001024,value=30000
EDMA REGS:name=EECR,addr=9001028,value=0
EDMA REGS:name=EECRH,addr=900102c,value=0
EDMA REGS:name=EESR,addr=9001030,value=0
EDMA REGS:name=EESRH,addr=9001034,value=0
EDMA REGS:name=SER,addr=9001038,value=100000
EDMA REGS:name=SERH,addr=900103c,value=0
EDMA REGS:name=SECR,addr=9001040,value=0
EDMA REGS:name=SECRH,addr=9001044,value=0
EDMA REGS:name=IER,addr=9001050,value=c0331704
EDMA REGS:name=IERH,addr=9001054,value=33c00
EDMA REGS:name=IECR,addr=9001058,value=0
EDMA REGS:name=IECRH,addr=900105c,value=0
EDMA REGS:name=IESR,addr=9001060,value=0
EDMA REGS:name=IESRH,addr=9001064,value=0
EDMA REGS:name=IPR,addr=9001068,value=0
EDMA REGS:name=IPRH,addr=900106c,value=0
EDMA REGS:name=ICR,addr=9001070,value=0
EDMA REGS:name=ICRH,addr=9001074,value=0
EDMA REGS:name=IEVAL,addr=9001078,value=0
EDMA REGS:name=QER,addr=9001080,value=0
EDMA REGS:name=QEER,addr=9001084,value=c0
EDMA REGS:name=QEECR,addr=9001088,value=0
EDMA REGS:name=QEESR,addr=900108c,value=0
EDMA REGS:name=QSER,addr=9001090,value=0
EDMA REGS:name=QSECR,addr=9001094,value=0
EDMA REGS:name=SHADOW[0].ER,addr=9002000,value=0
EDMA REGS:name=SHADOW[0].ERH,addr=9002004,value=0
EDMA REGS:name=SHADOW[0].ECR,addr=9002008,value=0
EDMA REGS:name=SHADOW[0].ECRH,addr=900200c,value=0
EDMA REGS:name=SHADOW[0].ESR,addr=9002010,value=0
EDMA REGS:name=SHADOW[0].ESRH,addr=9002014,value=0
EDMA REGS:name=SHADOW[0].CER,addr=9002018,value=0
EDMA REGS:name=SHADOW[0].CERH,addr=900201c,value=0
EDMA REGS:name=SHADOW[0].EER,addr=9002020,value=300000
EDMA REGS:name=SHADOW[0].EERH,addr=9002024,value=0
EDMA REGS:name=SHADOW[0].EECR,addr=9002028,value=0
EDMA REGS:name=SHADOW[0].EECRH,addr=900202c,value=0
EDMA REGS:name=SHADOW[0].EESR,addr=9002030,value=0
EDMA REGS:name=SHADOW[0].EESRH,addr=9002034,value=0
EDMA REGS:name=SHADOW[0].SER,addr=9002038,value=100000
EDMA REGS:name=SHADOW[0].SERH,addr=900203c,value=0
EDMA REGS:name=SHADOW[0].SECR,addr=9002040,value=0
EDMA REGS:name=SHADOW[0].SECRH,addr=9002044,value=0
EDMA REGS:name=SHADOW[0].IER,addr=9002050,value=c0330004
EDMA REGS:name=SHADOW[0].IERH,addr=9002054,value=3c00
EDMA REGS:name=SHADOW[0].IECR,addr=9002058,value=0
EDMA REGS:name=SHADOW[0].IECRH,addr=900205c,value=0
EDMA REGS:name=SHADOW[0].IESR,addr=9002060,value=0
EDMA REGS:name=SHADOW[0].IESRH,addr=9002064,value=0
EDMA REGS:name=SHADOW[0].IPR,addr=9002068,value=0
EDMA REGS:name=SHADOW[0].IPRH,addr=900206c,value=0
EDMA REGS:name=SHADOW[0].ICR,addr=9002070,value=0
EDMA REGS:name=SHADOW[0].ICRH,addr=9002074,value=0
EDMA REGS:name=SHADOW[0].IEVAL,addr=9002078,value=0
EDMA REGS:name=SHADOW[0].QER,addr=9002080,value=0
EDMA REGS:name=SHADOW[0].QEER,addr=9002084,value=c0
EDMA REGS:name=SHADOW[0].QEECR,addr=9002088,value=0
EDMA REGS:name=SHADOW[0].QEESR,addr=900208c,value=0
EDMA REGS:name=SHADOW[0].QSER,addr=9002090,value=0
EDMA REGS:name=SHADOW[0].QSECR,addr=9002094,value=0
EDMA REGS:name=SHADOW[1].ER,addr=9002200,value=0
EDMA REGS:name=SHADOW[1].ERH,addr=9002204,value=0
EDMA REGS:name=SHADOW[1].ECR,addr=9002208,value=0
EDMA REGS:name=SHADOW[1].ECRH,addr=900220c,value=0
EDMA REGS:name=SHADOW[1].ESR,addr=9002210,value=0
EDMA REGS:name=SHADOW[1].ESRH,addr=9002214,value=0
EDMA REGS:name=SHADOW[1].CER,addr=9002218,value=0
EDMA REGS:name=SHADOW[1].CERH,addr=900221c,value=0
EDMA REGS:name=SHADOW[1].EER,addr=9002220,value=1700
EDMA REGS:name=SHADOW[1].EERH,addr=9002224,value=30000
EDMA REGS:name=SHADOW[1].EECR,addr=9002228,value=0
EDMA REGS:name=SHADOW[1].EECRH,addr=900222c,value=0
EDMA REGS:name=SHADOW[1].EESR,addr=9002230,value=0
EDMA REGS:name=SHADOW[1].EESRH,addr=9002234,value=0
EDMA REGS:name=SHADOW[1].SER,addr=9002238,value=0
EDMA REGS:name=SHADOW[1].SERH,addr=900223c,value=0
EDMA REGS:name=SHADOW[1].SECR,addr=9002240,value=0
EDMA REGS:name=SHADOW[1].SECRH,addr=9002244,value=0
EDMA REGS:name=SHADOW[1].IER,addr=9002250,value=1704
EDMA REGS:name=SHADOW[1].IERH,addr=9002254,value=30000
EDMA REGS:name=SHADOW[1].IECR,addr=9002258,value=0
EDMA REGS:name=SHADOW[1].IECRH,addr=900225c,value=0
EDMA REGS:name=SHADOW[1].IESR,addr=9002260,value=0
EDMA REGS:name=SHADOW[1].IESRH,addr=9002264,value=0
EDMA REGS:name=SHADOW[1].IPR,addr=9002268,value=0
EDMA REGS:name=SHADOW[1].IPRH,addr=900226c,value=0
EDMA REGS:name=SHADOW[1].ICR,addr=9002270,value=0
EDMA REGS:name=SHADOW[1].ICRH,addr=9002274,value=0
EDMA REGS:name=SHADOW[1].IEVAL,addr=9002278,value=0
EDMA REGS:name=SHADOW[1].QER,addr=9002280,value=0
EDMA REGS:name=SHADOW[1].QEER,addr=9002284,value=0
EDMA REGS:name=SHADOW[1].QEECR,addr=9002288,value=0
EDMA REGS:name=SHADOW[1].QEESR,addr=900228c,value=0
EDMA REGS:name=SHADOW[1].QSER,addr=9002290,value=0
EDMA REGS:name=SHADOW[1].QSECR,addr=9002294,value=0

DSP is using channel 0x3, ARM is using channel 0x6\0x7\0x20\0x21.The PaRAM of these channels are as below.
//                                ch,     address, OPT,         SRC,         A_B_CNT, DST,         SRC_DST_BIDX, LINK_BCNTRLD, SRC_DST_CIDX,CCNT
EDMA PaRAM ch3: =3,     9004060, 8010300c, 81da20,    20020,       81db20,    200020,               2ffff,                      0,                         1
EDMA PaRAM ch6: =1c0, 9007800, 8011f00c, 8ccff00e,   660001,    2bf8900e, 10001,                  ffff,                         0,                       1
EDMA PaRAM ch7: =1e0, 9007C00,8011e00c, 2bf52800, a20001,    8cdc5000, 10001,                  ffff,                         0,                       1
EDMA PaRAM ch14:=14,   9004280, 0,               0,               0,              0,              0,                         ffff,                         0,                       0
EDMA PaRAM ch15:=15,   90042A0, 80115004, 481a413c,100001,     8e2ea080, 10000,                 1050c0,                 100000,             4

2. To avoid cache coherency problem,I put dbg_DMA_src_buf and dbg_DMA_dst_buf in L2 RAM(address of them are 0x81da20 and 0x81db20),
but the content of dbg_DMA_dst_buf still don't change after DMA transfer.

Best Regards

Hong

0 RandyP over 12 years ago in reply to Qiu Hong

TI__Guru* 84110 points

Hong,

This is an excellent register dump. If you are able and willing to share the script or code that generated it, many users may benefit from your work.

There are a few questions and concerns that I have. The first (#1) is likely the cause of the problem, but since I do not have access to the DRA6xx datasheet (and it must not be posted to this forum), I cannot be sure of the solution. Here is my list:

1. The DSP's L2 memory is usually accessed by two different addresses. The address range starting at 0x00800000 is called the Local L2 address and can only be used by the DSP when executing code. There is also an Global L2 address that may start at 0x11800000 or 0x40800000, or some other value, and this is the address that other bus masters may use to access the DSP's L2 memory. The EDMA3 module, in particular, must use the Global L2 address range to access this memory area. Please refer to your device's datasheet to find the Memory Map information that will tell you what the global address range is for the DSP's L2 memory.

2. Which DSP core is in your device? You said C67x, but I am not aware of any EDMA3 architectures that would have supported the old C67x. Is it the C674x? Or the C67x+?

3. Which ARM core is in your device? It may be the ARM926, ARM968, ARM7, ARM Cortex-A8, or ARM Cortex-M3, for example.

4. You did not include DCHMAP registers. Some devices do not have this, but it looks like you have mapped DMA Channel 6 to PARAM number 0x1c0. If you did not include DCHMAP because there are so many, that was probably a good choice. I wanted to confirm this.

5. A bit in EMR is set, which indicates that an event was missed. This is for channel 20, so it is not directly related to the current problem.

6. In most cases, the values in the DRAE/H registers should be mutually exclusive so that only one region may access any given channel. You have some bits that are set in both DRAE[0] and DRAE[1].

Regards,
RandyP

0 Qiu Hong over 12 years ago in reply to RandyP

Prodigy 100 points

Hi,RandyP

Good news.

1. After I use global L2 address 0x40000000, I can see value in dbg_DMA_dst_buf changed afte DMA data transfer.

2. After I make DRAE/H registers mutually exclusive , the manual trigged DMA will not fail. Before I change this, I find value in dbg_DMA_dst_buf may have changed but the

semaphore is not sent out sometimes.

3. The c code for dump registers is as below.

Fullscreen 6175.dumpRegsters.c Download

/*The CSL_Edma3ccRegs struct is provided by TI, a sample is as below. The init of g_edma_regs must be mapped to CSL_Edma3ccRegs struct. */

#define offsetof(s, m)   (uint)&(((s *)EDMA_CC_BASE)->m)

 typedef struct 
 {
     char name[30];
     Uint* address;
 }EDMA_regs_print_str;

typedef struct  {
    volatile Uint32 PID;
    volatile Uint32 CCCFG;
    volatile Uint8 RSVD0[504];
    volatile Uint32 QCHMAP[8];
    volatile Uint8 RSVD1[32];
    volatile Uint32 DMAQNUM[8];
    volatile Uint32 QDMAQNUM;
    volatile Uint8 RSVD2[32];
    volatile Uint32 QUEPRI;
    volatile Uint8 RSVD3[120];
    volatile Uint32 EMR;
    volatile Uint32 EMRH;
    volatile Uint32 EMCR;
    volatile Uint32 EMCRH;
    volatile Uint32 QEMR;
    volatile Uint32 QEMCR;
    volatile Uint32 CCERR;
    volatile Uint32 CCERRCLR;
    volatile Uint32 EEVAL;
    volatile Uint8 RSVD4[28];
    CSL_Edma3ccDraRegs DRA[8];
    volatile Uint32 QRAE[8];
    volatile Uint8 RSVD6[120-24];
    CSL_Edma3ccQueevtentryRegs QUEEVTENTRY[4];
    volatile Uint8 RSVD7[212+44];
    volatile Uint32 QSTAT[4];
    volatile Uint8 RSVD8[20-4];
    volatile Uint32 QWMTHRA;
    volatile Uint32 QWMTHRB;
    volatile Uint8 RSVD9[24];
    volatile Uint32 CCSTAT;
    volatile Uint8 RSVD10[188];
    volatile Uint32 AETCTL;
    volatile Uint32 AETSTAT;
    volatile Uint32 AETCMD;
    volatile Uint8 RSVD11[244];
    volatile Uint32 MPFAR;
    volatile Uint32 MPFSR;
    volatile Uint32 MPFCR;
    volatile Uint32 MPPA;
    volatile Uint8 RSVD12[2032];
    volatile Uint32 ER;
    volatile Uint32 ERH;
    volatile Uint32 ECR;
    volatile Uint32 ECRH;
    volatile Uint32 ESR;
    volatile Uint32 ESRH;
    volatile Uint32 CER;
    volatile Uint32 CERH;
    volatile Uint32 EER;
    volatile Uint32 EERH;
    volatile Uint32 EECR;
    volatile Uint32 EECRH;
    volatile Uint32 EESR;
    volatile Uint32 EESRH;
    volatile Uint32 SER;
    volatile Uint32 SERH;
    volatile Uint32 SECR;
    volatile Uint32 SECRH;
    volatile Uint8 RSVD13[8];
    volatile Uint32 IER;
    volatile Uint32 IERH;
    volatile Uint32 IECR;
    volatile Uint32 IECRH;
    volatile Uint32 IESR;
    volatile Uint32 IESRH;
    volatile Uint32 IPR;
    volatile Uint32 IPRH;
    volatile Uint32 ICR;
    volatile Uint32 ICRH;
    volatile Uint32 IEVAL;
    volatile Uint8 RSVD14[4];
    volatile Uint32 QER;
    volatile Uint32 QEER;
    volatile Uint32 QEECR;
    volatile Uint32 QEESR;
    volatile Uint32 QSER;
    volatile Uint32 QSECR;
    volatile Uint8 RSVD16[3944];
    CSL_Edma3ccShadowRegs SHADOW[2];
    volatile Uint8 RSVD18[7168];
    CSL_Edma3ccParamentryRegs PARAMENTRY[128];
} CSL_Edma3ccRegs;


EDMA_regs_print_str g_edma_regs[] = {
 {"PID",(uint*)(offsetof(CSL_Edma3ccRegs,PID))},
  {"CCCFG",(uint*)(offsetof(CSL_Edma3ccRegs,CCCFG))},
  {"QCHMAP[0]",(uint*)(offsetof(CSL_Edma3ccRegs,QCHMAP[0]))},
  {"QCHMAP[1]",(uint*)(offsetof(CSL_Edma3ccRegs,QCHMAP[1]))},
  {"QCHMAP[2]",(uint*)(offsetof(CSL_Edma3ccRegs,QCHMAP[2]))},
  {"QCHMAP[3]",(uint*)(offsetof(CSL_Edma3ccRegs,QCHMAP[3]))},
  {"QCHMAP[4]",(uint*)(offsetof(CSL_Edma3ccRegs,QCHMAP[4]))},
  {"QCHMAP[5]",(uint*)(offsetof(CSL_Edma3ccRegs,QCHMAP[5]))},
  {"QCHMAP[6]",(uint*)(offsetof(CSL_Edma3ccRegs,QCHMAP[6]))},
  {"QCHMAP[7]",(uint*)(offsetof(CSL_Edma3ccRegs,QCHMAP[7]))},
  {"DMAQNUM[0]",(uint*)(offsetof(CSL_Edma3ccRegs,DMAQNUM[0]))},
  {"DMAQNUM[1]",(uint*)(offsetof(CSL_Edma3ccRegs,DMAQNUM[1]))},
  {"DMAQNUM[2]",(uint*)(offsetof(CSL_Edma3ccRegs,DMAQNUM[2]))},
  {"DMAQNUM[3]",(uint*)(offsetof(CSL_Edma3ccRegs,DMAQNUM[3]))},
  {"DMAQNUM[4]",(uint*)(offsetof(CSL_Edma3ccRegs,DMAQNUM[4]))},
  {"DMAQNUM[5]",(uint*)(offsetof(CSL_Edma3ccRegs,DMAQNUM[5]))},
  {"DMAQNUM[6]",(uint*)(offsetof(CSL_Edma3ccRegs,DMAQNUM[6]))},
  {"DMAQNUM[7]",(uint*)(offsetof(CSL_Edma3ccRegs,DMAQNUM[7]))},
  {"QDMAQNUM",(uint*)(offsetof(CSL_Edma3ccRegs,QDMAQNUM))},
  {"QUEPRI",(uint*)(offsetof(CSL_Edma3ccRegs,QUEPRI))},
  {"EMR",(uint*)(offsetof(CSL_Edma3ccRegs,EMR))},
  {"EMRH",(uint*)(offsetof(CSL_Edma3ccRegs,EMRH))},
  {"EMCR",(uint*)(offsetof(CSL_Edma3ccRegs,EMCR))},
  {"EMCRH",(uint*)(offsetof(CSL_Edma3ccRegs,EMCRH))},
  {"QEMR",(uint*)(offsetof(CSL_Edma3ccRegs,QEMR))},
  {"QEMCR",(uint*)(offsetof(CSL_Edma3ccRegs,QEMCR))},
  {"CCERR",(uint*)(offsetof(CSL_Edma3ccRegs,CCERR))},
  {"CCERRCLR",(uint*)(offsetof(CSL_Edma3ccRegs,CCERRCLR))},
  {"EEVAL",(uint*)(offsetof(CSL_Edma3ccRegs,EEVAL))},
  {"DRA[0].DRAE",(uint*)(offsetof(CSL_Edma3ccRegs,DRA[0].DRAE))},
  {"DRA[0].DRAEH",(uint*)(offsetof(CSL_Edma3ccRegs,DRA[0].DRAEH))},
  {"DRA[1].DRAE",(uint*)(offsetof(CSL_Edma3ccRegs,DRA[1].DRAE))},
  {"DRA[1].DRAEH",(uint*)(offsetof(CSL_Edma3ccRegs,DRA[1].DRAEH))},
  {"DRA[2].DRAE",(uint*)(offsetof(CSL_Edma3ccRegs,DRA[2].DRAE))},
  {"DRA[2].DRAEH",(uint*)(offsetof(CSL_Edma3ccRegs,DRA[2].DRAEH))},
  {"DRA[3].DRAE",(uint*)(offsetof(CSL_Edma3ccRegs,DRA[3].DRAE))},
  {"DRA[3].DRAEH",(uint*)(offsetof(CSL_Edma3ccRegs,DRA[3].DRAEH))},
  {"DRA[4].DRAE",(uint*)(offsetof(CSL_Edma3ccRegs,DRA[4].DRAE))},
  {"DRA[4].DRAEH",(uint*)(offsetof(CSL_Edma3ccRegs,DRA[4].DRAEH))},
  {"DRA[5].DRAE",(uint*)(offsetof(CSL_Edma3ccRegs,DRA[5].DRAE))},
  {"DRA[5].DRAEH",(uint*)(offsetof(CSL_Edma3ccRegs,DRA[5].DRAEH))},
  {"DRA[6].DRAE",(uint*)(offsetof(CSL_Edma3ccRegs,DRA[6].DRAE))},
  {"DRA[6].DRAEH",(uint*)(offsetof(CSL_Edma3ccRegs,DRA[6].DRAEH))},
  {"DRA[7].DRAE",(uint*)(offsetof(CSL_Edma3ccRegs,DRA[7].DRAE))},
  {"DRA[7].DRAEH",(uint*)(offsetof(CSL_Edma3ccRegs,DRA[7].DRAEH))},
  {"QRAE[0]",(uint*)(offsetof(CSL_Edma3ccRegs,QRAE[0]))},
  {"QRAE[1]",(uint*)(offsetof(CSL_Edma3ccRegs,QRAE[1]))},
  {"QRAE[2]",(uint*)(offsetof(CSL_Edma3ccRegs,QRAE[2]))},
  {"QRAE[3]",(uint*)(offsetof(CSL_Edma3ccRegs,QRAE[3]))},
  {"QRAE[4]",(uint*)(offsetof(CSL_Edma3ccRegs,QRAE[4]))},
  {"QRAE[5]",(uint*)(offsetof(CSL_Edma3ccRegs,QRAE[5]))},
  {"QRAE[6]",(uint*)(offsetof(CSL_Edma3ccRegs,QRAE[6]))},
  {"QRAE[7]",(uint*)(offsetof(CSL_Edma3ccRegs,QRAE[7]))},
  {"QUEEVTENTRY[0].QUEEVT[0]",(uint*)(offsetof(CSL_Edma3ccRegs,QUEEVTENTRY[0].QUEEVT_ENTRY[0] ))},
  {"QUEEVTENTRY[0].QUEEVT[1]",(uint*)(offsetof(CSL_Edma3ccRegs,QUEEVTENTRY[0].QUEEVT_ENTRY[1] ))},
  {"QUEEVTENTRY[0].QUEEVT[2]",(uint*)(offsetof(CSL_Edma3ccRegs,QUEEVTENTRY[0].QUEEVT_ENTRY[2] ))},
  {"QUEEVTENTRY[0].QUEEVT[3]",(uint*)(offsetof(CSL_Edma3ccRegs,QUEEVTENTRY[0].QUEEVT_ENTRY[3] ))},
  {"QUEEVTENTRY[0].QUEEVT[4]",(uint*)(offsetof(CSL_Edma3ccRegs,QUEEVTENTRY[0].QUEEVT_ENTRY[4] ))},
  {"QUEEVTENTRY[0].QUEEVT[5]",(uint*)(offsetof(CSL_Edma3ccRegs,QUEEVTENTRY[0].QUEEVT_ENTRY[5] ))},
  {"QUEEVTENTRY[0].QUEEVT[6]",(uint*)(offsetof(CSL_Edma3ccRegs,QUEEVTENTRY[0].QUEEVT_ENTRY[6] ))},
  {"QUEEVTENTRY[0].QUEEVT[7]",(uint*)(offsetof(CSL_Edma3ccRegs,QUEEVTENTRY[0].QUEEVT_ENTRY[7] ))},
  {"QUEEVTENTRY[0].QUEEVT[8]",(uint*)(offsetof(CSL_Edma3ccRegs,QUEEVTENTRY[0].QUEEVT_ENTRY[8] ))},
  {"QUEEVTENTRY[0].QUEEVT[9]",(uint*)(offsetof(CSL_Edma3ccRegs,QUEEVTENTRY[0].QUEEVT_ENTRY[9] ))},
  {"QUEEVTENTRY[0].QUEEVT[10]",(uint*)(offsetof(CSL_Edma3ccRegs,QUEEVTENTRY[0].QUEEVT_ENTRY[10] ))},
  {"QUEEVTENTRY[0].QUEEVT[11]",(uint*)(offsetof(CSL_Edma3ccRegs,QUEEVTENTRY[0].QUEEVT_ENTRY[11] ))},
  {"QUEEVTENTRY[0].QUEEVT[12]",(uint*)(offsetof(CSL_Edma3ccRegs,QUEEVTENTRY[0].QUEEVT_ENTRY[12] ))},
  {"QUEEVTENTRY[0].QUEEVT[13]",(uint*)(offsetof(CSL_Edma3ccRegs,QUEEVTENTRY[0].QUEEVT_ENTRY[13] ))},
  {"QUEEVTENTRY[0].QUEEVT[14]",(uint*)(offsetof(CSL_Edma3ccRegs,QUEEVTENTRY[0].QUEEVT_ENTRY[14] ))},
  {"QUEEVTENTRY[0].QUEEVT[15]",(uint*)(offsetof(CSL_Edma3ccRegs,QUEEVTENTRY[0].QUEEVT_ENTRY[15] ))},
  {"QUEEVTENTRY[1].QUEEVT[0]",(uint*)(offsetof(CSL_Edma3ccRegs,QUEEVTENTRY[1].QUEEVT_ENTRY[0] ))},
  {"QUEEVTENTRY[1].QUEEVT[1]",(uint*)(offsetof(CSL_Edma3ccRegs,QUEEVTENTRY[1].QUEEVT_ENTRY[1] ))},
  {"QUEEVTENTRY[1].QUEEVT[2]",(uint*)(offsetof(CSL_Edma3ccRegs,QUEEVTENTRY[1].QUEEVT_ENTRY[2] ))},
  {"QUEEVTENTRY[1].QUEEVT[3]",(uint*)(offsetof(CSL_Edma3ccRegs,QUEEVTENTRY[1].QUEEVT_ENTRY[3] ))},
  {"QUEEVTENTRY[1].QUEEVT[4]",(uint*)(offsetof(CSL_Edma3ccRegs,QUEEVTENTRY[1].QUEEVT_ENTRY[4] ))},
  {"QUEEVTENTRY[1].QUEEVT[5]",(uint*)(offsetof(CSL_Edma3ccRegs,QUEEVTENTRY[1].QUEEVT_ENTRY[5] ))},
  {"QUEEVTENTRY[1].QUEEVT[6]",(uint*)(offsetof(CSL_Edma3ccRegs,QUEEVTENTRY[1].QUEEVT_ENTRY[6] ))},
  {"QUEEVTENTRY[1].QUEEVT[7]",(uint*)(offsetof(CSL_Edma3ccRegs,QUEEVTENTRY[1].QUEEVT_ENTRY[7] ))},
  {"QUEEVTENTRY[1].QUEEVT[8]",(uint*)(offsetof(CSL_Edma3ccRegs,QUEEVTENTRY[1].QUEEVT_ENTRY[8] ))},
  {"QUEEVTENTRY[1].QUEEVT[9]",(uint*)(offsetof(CSL_Edma3ccRegs,QUEEVTENTRY[1].QUEEVT_ENTRY[9] ))},
  {"QUEEVTENTRY[1].QUEEVT[10]",(uint*)(offsetof(CSL_Edma3ccRegs,QUEEVTENTRY[1].QUEEVT_ENTRY[10] ))},
  {"QUEEVTENTRY[1].QUEEVT[11]",(uint*)(offsetof(CSL_Edma3ccRegs,QUEEVTENTRY[1].QUEEVT_ENTRY[11] ))},
  {"QUEEVTENTRY[1].QUEEVT[12]",(uint*)(offsetof(CSL_Edma3ccRegs,QUEEVTENTRY[1].QUEEVT_ENTRY[12] ))},
  {"QUEEVTENTRY[1].QUEEVT[13]",(uint*)(offsetof(CSL_Edma3ccRegs,QUEEVTENTRY[1].QUEEVT_ENTRY[13] ))},
  {"QUEEVTENTRY[1].QUEEVT[14]",(uint*)(offsetof(CSL_Edma3ccRegs,QUEEVTENTRY[1].QUEEVT_ENTRY[14] ))},
  {"QUEEVTENTRY[1].QUEEVT[15]",(uint*)(offsetof(CSL_Edma3ccRegs,QUEEVTENTRY[1].QUEEVT_ENTRY[15] ))},
  {"QUEEVTENTRY[2].QUEEVT[0]",(uint*)(offsetof(CSL_Edma3ccRegs,QUEEVTENTRY[2].QUEEVT_ENTRY[0] ))},
  {"QUEEVTENTRY[2].QUEEVT[1]",(uint*)(offsetof(CSL_Edma3ccRegs,QUEEVTENTRY[2].QUEEVT_ENTRY[1] ))},
  {"QUEEVTENTRY[2].QUEEVT[2]",(uint*)(offsetof(CSL_Edma3ccRegs,QUEEVTENTRY[2].QUEEVT_ENTRY[2] ))},
  {"QUEEVTENTRY[2].QUEEVT[3]",(uint*)(offsetof(CSL_Edma3ccRegs,QUEEVTENTRY[2].QUEEVT_ENTRY[3] ))},
  {"QUEEVTENTRY[2].QUEEVT[4]",(uint*)(offsetof(CSL_Edma3ccRegs,QUEEVTENTRY[2].QUEEVT_ENTRY[4] ))},
  {"QUEEVTENTRY[2].QUEEVT[5]",(uint*)(offsetof(CSL_Edma3ccRegs,QUEEVTENTRY[2].QUEEVT_ENTRY[5] ))},
  {"QUEEVTENTRY[2].QUEEVT[6]",(uint*)(offsetof(CSL_Edma3ccRegs,QUEEVTENTRY[2].QUEEVT_ENTRY[6] ))},
  {"QUEEVTENTRY[2].QUEEVT[7]",(uint*)(offsetof(CSL_Edma3ccRegs,QUEEVTENTRY[2].QUEEVT_ENTRY[7] ))},
  {"QUEEVTENTRY[2].QUEEVT[8]",(uint*)(offsetof(CSL_Edma3ccRegs,QUEEVTENTRY[2].QUEEVT_ENTRY[8] ))},
  {"QUEEVTENTRY[2].QUEEVT[9]",(uint*)(offsetof(CSL_Edma3ccRegs,QUEEVTENTRY[2].QUEEVT_ENTRY[9] ))},
  {"QUEEVTENTRY[2].QUEEVT[10]",(uint*)(offsetof(CSL_Edma3ccRegs,QUEEVTENTRY[2].QUEEVT_ENTRY[10] ))},
  {"QUEEVTENTRY[2].QUEEVT[11]",(uint*)(offsetof(CSL_Edma3ccRegs,QUEEVTENTRY[2].QUEEVT_ENTRY[11] ))},
  {"QUEEVTENTRY[2].QUEEVT[12]",(uint*)(offsetof(CSL_Edma3ccRegs,QUEEVTENTRY[2].QUEEVT_ENTRY[12] ))},
  {"QUEEVTENTRY[2].QUEEVT[13]",(uint*)(offsetof(CSL_Edma3ccRegs,QUEEVTENTRY[2].QUEEVT_ENTRY[13] ))},
  {"QUEEVTENTRY[2].QUEEVT[14]",(uint*)(offsetof(CSL_Edma3ccRegs,QUEEVTENTRY[2].QUEEVT_ENTRY[14] ))},
  {"QUEEVTENTRY[2].QUEEVT[15]",(uint*)(offsetof(CSL_Edma3ccRegs,QUEEVTENTRY[2].QUEEVT_ENTRY[15] ))},
  {"QUEEVTENTRY[3].QUEEVT[0]",(uint*)(offsetof(CSL_Edma3ccRegs,QUEEVTENTRY[3].QUEEVT_ENTRY[0] ))},
  {"QUEEVTENTRY[3].QUEEVT[1]",(uint*)(offsetof(CSL_Edma3ccRegs,QUEEVTENTRY[3].QUEEVT_ENTRY[1] ))},
  {"QUEEVTENTRY[3].QUEEVT[2]",(uint*)(offsetof(CSL_Edma3ccRegs,QUEEVTENTRY[3].QUEEVT_ENTRY[2] ))},
  {"QUEEVTENTRY[3].QUEEVT[3]",(uint*)(offsetof(CSL_Edma3ccRegs,QUEEVTENTRY[3].QUEEVT_ENTRY[3] ))},
  {"QUEEVTENTRY[3].QUEEVT[4]",(uint*)(offsetof(CSL_Edma3ccRegs,QUEEVTENTRY[3].QUEEVT_ENTRY[4] ))},
  {"QUEEVTENTRY[3].QUEEVT[5]",(uint*)(offsetof(CSL_Edma3ccRegs,QUEEVTENTRY[3].QUEEVT_ENTRY[5] ))},
  {"QUEEVTENTRY[3].QUEEVT[6]",(uint*)(offsetof(CSL_Edma3ccRegs,QUEEVTENTRY[3].QUEEVT_ENTRY[6] ))},
  {"QUEEVTENTRY[3].QUEEVT[7]",(uint*)(offsetof(CSL_Edma3ccRegs,QUEEVTENTRY[3].QUEEVT_ENTRY[7] ))},
  {"QUEEVTENTRY[3].QUEEVT[8]",(uint*)(offsetof(CSL_Edma3ccRegs,QUEEVTENTRY[3].QUEEVT_ENTRY[8] ))},
  {"QUEEVTENTRY[3].QUEEVT[9]",(uint*)(offsetof(CSL_Edma3ccRegs,QUEEVTENTRY[3].QUEEVT_ENTRY[9] ))},
  {"QUEEVTENTRY[3].QUEEVT[10]",(uint*)(offsetof(CSL_Edma3ccRegs,QUEEVTENTRY[3].QUEEVT_ENTRY[10] ))},
  {"QUEEVTENTRY[3].QUEEVT[11]",(uint*)(offsetof(CSL_Edma3ccRegs,QUEEVTENTRY[3].QUEEVT_ENTRY[11] ))},
  {"QUEEVTENTRY[3].QUEEVT[12]",(uint*)(offsetof(CSL_Edma3ccRegs,QUEEVTENTRY[3].QUEEVT_ENTRY[12] ))},
  {"QUEEVTENTRY[3].QUEEVT[13]",(uint*)(offsetof(CSL_Edma3ccRegs,QUEEVTENTRY[3].QUEEVT_ENTRY[13] ))},
  {"QUEEVTENTRY[3].QUEEVT[14]",(uint*)(offsetof(CSL_Edma3ccRegs,QUEEVTENTRY[3].QUEEVT_ENTRY[14] ))},
  {"QUEEVTENTRY[3].QUEEVT[15]",(uint*)(offsetof(CSL_Edma3ccRegs,QUEEVTENTRY[3].QUEEVT_ENTRY[15] ))}, 
  {"QSTAT[0]",(uint*)(offsetof(CSL_Edma3ccRegs,QSTAT[0]))},
  {"QSTAT[1]",(uint*)(offsetof(CSL_Edma3ccRegs,QSTAT[1]))},
  {"QSTAT[2]",(uint*)(offsetof(CSL_Edma3ccRegs,QSTAT[2]))},
  {"QSTAT[3]",(uint*)(offsetof(CSL_Edma3ccRegs,QSTAT[3]))},
  {"QWMTHRA",(uint*)(offsetof(CSL_Edma3ccRegs,QWMTHRA))},
  {"QWMTHRB",(uint*)(offsetof(CSL_Edma3ccRegs,QWMTHRB))},
  {"CCSTAT",(uint*)(offsetof(CSL_Edma3ccRegs,CCSTAT))},
  {"AETCTL",(uint*)(offsetof(CSL_Edma3ccRegs,AETCTL))},
  {"AETSTAT",(uint*)(offsetof(CSL_Edma3ccRegs,AETSTAT))},
  {"AETCMD",(uint*)(offsetof(CSL_Edma3ccRegs,AETCMD))},
  {"MPFAR",(uint*)(offsetof(CSL_Edma3ccRegs,MPFAR))},
  {"MPFSR",(uint*)(offsetof(CSL_Edma3ccRegs,MPFSR))},
  {"MPFCR",(uint*)(offsetof(CSL_Edma3ccRegs,MPFCR))}, 
  {"MPPA",(uint*)(offsetof(CSL_Edma3ccRegs,MPPA))}, 
  {"ER",(uint*)(offsetof(CSL_Edma3ccRegs,ER))}, 
  {"ERH",(uint*)(offsetof(CSL_Edma3ccRegs,ERH))}, 
  {"ECR",(uint*)(offsetof(CSL_Edma3ccRegs,ECR))}, 
  {"ECRH",(uint*)(offsetof(CSL_Edma3ccRegs,ECRH))}, 
  {"ESR",(uint*)(offsetof(CSL_Edma3ccRegs,ESR))}, 
  {"ESRH",(uint*)(offsetof(CSL_Edma3ccRegs,ESRH))}, 
  {"CER",(uint*)(offsetof(CSL_Edma3ccRegs,CER))}, 
  {"CERH",(uint*)(offsetof(CSL_Edma3ccRegs,CERH))}, 
  {"EER",(uint*)(offsetof(CSL_Edma3ccRegs,EER))}, 
  {"EERH",(uint*)(offsetof(CSL_Edma3ccRegs,EERH))}, 
  {"EECR",(uint*)(offsetof(CSL_Edma3ccRegs,EECR))}, 
  {"EECRH",(uint*)(offsetof(CSL_Edma3ccRegs,EECRH))}, 
  {"EESR",(uint*)(offsetof(CSL_Edma3ccRegs,EESR))}, 
  {"EESRH",(uint*)(offsetof(CSL_Edma3ccRegs,EESRH))}, 
  {"SER",(uint*)(offsetof(CSL_Edma3ccRegs,SER))}, 
  {"SERH",(uint*)(offsetof(CSL_Edma3ccRegs,SERH))}, 
  {"SECR",(uint*)(offsetof(CSL_Edma3ccRegs,SECR))}, 
  {"SECRH",(uint*)(offsetof(CSL_Edma3ccRegs,SECRH))}, 
  {"IER",(uint*)(offsetof(CSL_Edma3ccRegs,IER))}, 
  {"IERH",(uint*)(offsetof(CSL_Edma3ccRegs,IERH))}, 
  {"IECR",(uint*)(offsetof(CSL_Edma3ccRegs,IECR))}, 
  {"IECRH",(uint*)(offsetof(CSL_Edma3ccRegs,IECRH))}, 
  {"IESR",(uint*)(offsetof(CSL_Edma3ccRegs,IESR))}, 
  {"IESRH",(uint*)(offsetof(CSL_Edma3ccRegs,IESRH))}, 
  {"IPR",(uint*)(offsetof(CSL_Edma3ccRegs,IPR))}, 
  {"IPRH",(uint*)(offsetof(CSL_Edma3ccRegs,IPRH))}, 
  {"ICR",(uint*)(offsetof(CSL_Edma3ccRegs,ICR))}, 
  {"ICRH",(uint*)(offsetof(CSL_Edma3ccRegs,ICRH))}, 
  {"IEVAL",(uint*)(offsetof(CSL_Edma3ccRegs,IEVAL))}, 
  {"QER",(uint*)(offsetof(CSL_Edma3ccRegs,QER))}, 
  {"QEER",(uint*)(offsetof(CSL_Edma3ccRegs,QEER))}, 
  {"QEECR",(uint*)(offsetof(CSL_Edma3ccRegs,QEECR))}, 
  {"QEESR",(uint*)(offsetof(CSL_Edma3ccRegs,QEESR))}, 
  {"QSER",(uint*)(offsetof(CSL_Edma3ccRegs,QSER))}, 
  {"QSECR",(uint*)(offsetof(CSL_Edma3ccRegs,QSECR))}, 
  {"SHADOW[0].ER",(uint*)(offsetof(CSL_Edma3ccRegs,SHADOW[0].ER))}, 
 {"SHADOW[0].ERH",(uint*)(offsetof(CSL_Edma3ccRegs,SHADOW[0].ERH))}, 
 {"SHADOW[0].ECR",(uint*)(offsetof(CSL_Edma3ccRegs,SHADOW[0].ECR))}, 
 {"SHADOW[0].ECRH",(uint*)(offsetof(CSL_Edma3ccRegs,SHADOW[0].ECRH))}, 
 {"SHADOW[0].ESR",(uint*)(offsetof(CSL_Edma3ccRegs,SHADOW[0].ECRH))}, 
 {"SHADOW[0].ESRH",(uint*)(offsetof(CSL_Edma3ccRegs,SHADOW[0].ESRH))}, 
 {"SHADOW[0].CER",(uint*)(offsetof(CSL_Edma3ccRegs,SHADOW[0].CER))}, 
 {"SHADOW[0].CERH",(uint*)(offsetof(CSL_Edma3ccRegs,SHADOW[0].CERH))}, 
 {"SHADOW[0].EER",(uint*)(offsetof(CSL_Edma3ccRegs,SHADOW[0].EER))}, 
 {"SHADOW[0].EERH",(uint*)(offsetof(CSL_Edma3ccRegs,SHADOW[0].EERH))}, 
 {"SHADOW[0].EECR",(uint*)(offsetof(CSL_Edma3ccRegs,SHADOW[0].EECR))}, 
 {"SHADOW[0].EECRH",(uint*)(offsetof(CSL_Edma3ccRegs,SHADOW[0].EECRH))}, 
 {"SHADOW[0].EESR",(uint*)(offsetof(CSL_Edma3ccRegs,SHADOW[0].EESR))}, 
 {"SHADOW[0].EESRH",(uint*)(offsetof(CSL_Edma3ccRegs,SHADOW[0].EESRH))}, 
 {"SHADOW[0].SER",(uint*)(offsetof(CSL_Edma3ccRegs,SHADOW[0].SER))}, 
 {"SHADOW[0].SERH",(uint*)(offsetof(CSL_Edma3ccRegs,SHADOW[0].SERH))}, 
 {"SHADOW[0].SECR",(uint*)(offsetof(CSL_Edma3ccRegs,SHADOW[0].SECR))}, 
 {"SHADOW[0].SECRH",(uint*)(offsetof(CSL_Edma3ccRegs,SHADOW[0].SECRH))}, 
 {"SHADOW[0].IER",(uint*)(offsetof(CSL_Edma3ccRegs,SHADOW[0].IER))}, 
 {"SHADOW[0].IERH",(uint*)(offsetof(CSL_Edma3ccRegs,SHADOW[0].IERH))}, 
 {"SHADOW[0].IECR",(uint*)(offsetof(CSL_Edma3ccRegs,SHADOW[0].IECR))}, 
 {"SHADOW[0].IECRH",(uint*)(offsetof(CSL_Edma3ccRegs,SHADOW[0].IECRH))}, 
 {"SHADOW[0].IESR",(uint*)(offsetof(CSL_Edma3ccRegs,SHADOW[0].IESR))}, 
 {"SHADOW[0].IESRH",(uint*)(offsetof(CSL_Edma3ccRegs,SHADOW[0].IESRH))}, 
 {"SHADOW[0].IPR",(uint*)(offsetof(CSL_Edma3ccRegs,SHADOW[0].IPR))}, 
 {"SHADOW[0].IPRH",(uint*)(offsetof(CSL_Edma3ccRegs,SHADOW[0].IPRH))}, 
 {"SHADOW[0].ICR",(uint*)(offsetof(CSL_Edma3ccRegs,SHADOW[0].ICR))}, 
  {"SHADOW[0].ICRH",(uint*)(offsetof(CSL_Edma3ccRegs,SHADOW[0].ICRH))}, 
  {"SHADOW[0].IEVAL",(uint*)(offsetof(CSL_Edma3ccRegs,SHADOW[0].IEVAL))}, 
  {"SHADOW[0].QER",(uint*)(offsetof(CSL_Edma3ccRegs,SHADOW[0].QER))}, 
  {"SHADOW[0].QEER",(uint*)(offsetof(CSL_Edma3ccRegs,SHADOW[0].QEER))}, 
  {"SHADOW[0].QEECR",(uint*)(offsetof(CSL_Edma3ccRegs,SHADOW[0].QEECR))}, 
  {"SHADOW[0].QEESR",(uint*)(offsetof(CSL_Edma3ccRegs,SHADOW[0].QEESR))}, 
  {"SHADOW[0].QSER",(uint*)(offsetof(CSL_Edma3ccRegs,SHADOW[0].QSER))}, 
  {"SHADOW[0].QSECR",(uint*)(offsetof(CSL_Edma3ccRegs,SHADOW[0].QSECR))}, 
  {"SHADOW[1].ER",(uint*)(offsetof(CSL_Edma3ccRegs,SHADOW[1].ER))}, 
 {"SHADOW[1].ERH",(uint*)(offsetof(CSL_Edma3ccRegs,SHADOW[1].ERH))}, 
 {"SHADOW[1].ECR",(uint*)(offsetof(CSL_Edma3ccRegs,SHADOW[1].ECR))}, 
 {"SHADOW[1].ECRH",(uint*)(offsetof(CSL_Edma3ccRegs,SHADOW[1].ECRH))}, 
 {"SHADOW[1].ESR",(uint*)(offsetof(CSL_Edma3ccRegs,SHADOW[1].ECRH))}, 
 {"SHADOW[1].ESRH",(uint*)(offsetof(CSL_Edma3ccRegs,SHADOW[1].ESRH))}, 
 {"SHADOW[1].CER",(uint*)(offsetof(CSL_Edma3ccRegs,SHADOW[1].CER))}, 
 {"SHADOW[1].CERH",(uint*)(offsetof(CSL_Edma3ccRegs,SHADOW[1].CERH))}, 
 {"SHADOW[1].EER",(uint*)(offsetof(CSL_Edma3ccRegs,SHADOW[1].EER))}, 
 {"SHADOW[1].EERH",(uint*)(offsetof(CSL_Edma3ccRegs,SHADOW[1].EERH))}, 
 {"SHADOW[1].EECR",(uint*)(offsetof(CSL_Edma3ccRegs,SHADOW[1].EECR))}, 
 {"SHADOW[1].EECRH",(uint*)(offsetof(CSL_Edma3ccRegs,SHADOW[1].EECRH))}, 
 {"SHADOW[1].EESR",(uint*)(offsetof(CSL_Edma3ccRegs,SHADOW[1].EESR))}, 
 {"SHADOW[1].EESRH",(uint*)(offsetof(CSL_Edma3ccRegs,SHADOW[1].EESRH))}, 
 {"SHADOW[1].SER",(uint*)(offsetof(CSL_Edma3ccRegs,SHADOW[1].SER))}, 
 {"SHADOW[1].SERH",(uint*)(offsetof(CSL_Edma3ccRegs,SHADOW[1].SERH))}, 
 {"SHADOW[1].SECR",(uint*)(offsetof(CSL_Edma3ccRegs,SHADOW[1].SECR))}, 
 {"SHADOW[1].SECRH",(uint*)(offsetof(CSL_Edma3ccRegs,SHADOW[1].SECRH))}, 
 {"SHADOW[1].IER",(uint*)(offsetof(CSL_Edma3ccRegs,SHADOW[1].IER))}, 
 {"SHADOW[1].IERH",(uint*)(offsetof(CSL_Edma3ccRegs,SHADOW[1].IERH))}, 
 {"SHADOW[1].IECR",(uint*)(offsetof(CSL_Edma3ccRegs,SHADOW[1].IECR))}, 
 {"SHADOW[1].IECRH",(uint*)(offsetof(CSL_Edma3ccRegs,SHADOW[1].IECRH))}, 
 {"SHADOW[1].IESR",(uint*)(offsetof(CSL_Edma3ccRegs,SHADOW[1].IESR))}, 
 {"SHADOW[1].IESRH",(uint*)(offsetof(CSL_Edma3ccRegs,SHADOW[1].IESRH))}, 
 {"SHADOW[1].IPR",(uint*)(offsetof(CSL_Edma3ccRegs,SHADOW[1].IPR))}, 
 {"SHADOW[1].IPRH",(uint*)(offsetof(CSL_Edma3ccRegs,SHADOW[1].IPRH))}, 
 {"SHADOW[1].ICR",(uint*)(offsetof(CSL_Edma3ccRegs,SHADOW[1].ICR))}, 
  {"SHADOW[1].ICRH",(uint*)(offsetof(CSL_Edma3ccRegs,SHADOW[1].ICRH))}, 
  {"SHADOW[1].IEVAL",(uint*)(offsetof(CSL_Edma3ccRegs,SHADOW[1].IEVAL))}, 
  {"SHADOW[1].QER",(uint*)(offsetof(CSL_Edma3ccRegs,SHADOW[1].QER))}, 
  {"SHADOW[1].QEER",(uint*)(offsetof(CSL_Edma3ccRegs,SHADOW[1].QEER))}, 
  {"SHADOW[1].QEECR",(uint*)(offsetof(CSL_Edma3ccRegs,SHADOW[1].QEECR))}, 
  {"SHADOW[1].QEESR",(uint*)(offsetof(CSL_Edma3ccRegs,SHADOW[1].QEESR))}, 
  {"SHADOW[1].QSER",(uint*)(offsetof(CSL_Edma3ccRegs,SHADOW[1].QSER))}, 
  {"SHADOW[1].QSECR",(uint*)(offsetof(CSL_Edma3ccRegs,SHADOW[1].QSECR))}?
 };

for(j=0; j<100; j++)
{
    sprintf(msg,"EDMA REGS:name=%s,addr=%x,value=%x",(g_edma_regs[j].name),(g_edma_regs[j].address),(*(g_edma_regs[j].address)));
}

0 RandyP over 12 years ago in reply to Qiu Hong

TI__Guru* 84110 points

Qiu,

Thank you for the success report, and for the dump code. I will save a copy of your post to refer others in the future.

Your code is very clean and structured. It will be useful for anyone to apply to any other register regions, also.

Is there a compiler benefit of the '?' at the end of line 333? Or is that just a forum-upload artifact?

Regards,
RandyP

0 Qiu Hong over 12 years ago in reply to RandyP

Prodigy 100 points

Hi, RandyP

Thanks for your help.

At the end of line 333? is my error.

Best Regards

Hong

Processors

Processors forum

EDMA manually-triggered transfer fail sometimes