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OMAP4470 DSI/DISPC timing configuration.

woogee Cheong
Prodigy 20 points
Other Parts Discussed in Thread: SYSCONFIG

Hi all,

I am porting MIPI DSI Panel with TC358764 on a custom board with OMAP4470. 

I configured DSI timings and panel settings with the recommended  value of TC358764 & Panel.

But, I don't know how to set DISPC_timing and so on. So I used the timing value in your reference source.

Now, the RESYNCHRONIZATION_IRQ is occurred continuously.

We checked the TRM document and found:
The RESYNCHRONIZATION_IRQ indicates software users that the video port works but the configuration of the timings for the display controller (DISPC) and for DSI Protocol engine may need to be modified to avoid the resynchronization to occur.

This is my current configuration.

* LCD Panel Specification

Resolution = 1280*720

Pixel Clock = 38.667MHz

HSW=224

HBP=200

HFP=26

VSW=12

VBP=12

VFP=3

* DSI_Timing

static struct omap_dsi_timings dsi_timings_tc35876x_hx7816 = {
.hbp = 10,
.hfp = 441,
.hsa = 0,
.vbp = 24,
.vfp = 3,
.vsa = 0,
.vact = 720,
.tl = 747,
.hsa_hs_int = 72,
.hfp_hs_int = 114,
.hbp_hs_int = 150,
.hsa_lp_int = 130,
.hfp_lp_int = 223,
.hbp_lp_int = 59,
.bl_lp_int = 0x31d1,
.bl_hs_int = 0x7a67,
.exit_lat = 15,
.enter_lat = 18,
};

*DISPC_timing

static struct omap_video_timings dispc_timings_tc35876x_hx7816 = {
.x_res = 1280,
.y_res = 720,
.hfp = 243,
.hsw = 9,
.hbp = 20,
.vfp = 6,
.vsw = 2,
.vbp = 4,

};

* DSS device settings

static struct omap_dss_device lcd_tc35876x_hx7816 = {
.name = "lcd",
.driver_name = "tc358765",
.type = OMAP_DISPLAY_TYPE_DSI,
.data = &dsi_data_tc35876x_hx7816,
.phy.dsi = {
.clk_lane = 1,
.clk_pol = 0,
.data1_lane = 2,
.data1_pol = 0,
.data2_lane = 3,
.data2_pol = 0,
//.data3_lane = 4,   // using 2 data lanes
//.data3_pol = 0,
//.data4_lane = 5, 
//.data4_pol = 0,

.type = OMAP_DSS_DSI_TYPE_VIDEO_MODE,
.line_bufs = 2,
},

.clocks = {
.dispc = {
.channel = {
.lck_div = 1, // woogee test 1,
.pck_div = 4, // woogee test 2,
.lcd_clk_src = OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC,
},
.dispc_fclk_src = OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC,
},

.dsi = {
.regn = 20,//38,//38, //16, //38,
.regm = 242,//441, //180, //441,
.regm_dispc = 6,//6, //5, //6,
.regm_dsi = 9, //5, //9,
.lp_clk_div = 4,//5, //10, //5,
.offset_ddr_clk = 0,
.dsi_fclk_src = OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI,
.tlpx = 12,
.tclk = {
.zero = 58, //57, //58,
.prepare = 15,
.trail = 16, //15, //16,
},
.ths = {
.zero = 23, //22, //23,
.prepare = 18,
.exit = 32, //32, //33,
.trail = 19, //18, //19,
},
},
},

.panel = {
.timings = {
.x_res = 1280,
.y_res = 720,
.pixel_clock = 38667,
.hfp = 26, 
.hsw = 224,
.hbp = 200,
.vfp = 3, 
.vsw = 12,
.vbp = 12,
},
.width_in_um = 217000,
.height_in_um = 135600,
},

.ctrl = {
.pixel_size = 24,
},

.reset_gpio = 102,
.channel = OMAP_DSS_CHANNEL_LCD,
.skip_init = false,

.platform_enable = NULL,
.platform_disable = NULL,
.dispc_timings = &dispc_timings_tc35876x_hx7816,
.dsi_timings = &dsi_timings_tc35876x_hx7816,
};

*OMAPDSS clock

shell@android:/d/omapdss # cat clk
cat clk
- DSS -
dpll4_ck 1536000000
DSS_FCK (DSS_FCLK) = 1536000000 / 9 = 170666666
- DISPC -
dispc fclk source = DSS_FCK (DSS_FCLK)
fck 170666666
- DISPC-CORE-CLK -
lck 170666666 lck div 1
- LCD1 -
lcd1_clk source = DSI_PLL_HSDIV_DISPC (PLL1_CLK1)
lck 154880000 lck div 1
pck 38720000 pck div 4
- LCD2 -
lcd2_clk source = DSS_FCK (DSS_FCLK)
lck 42666666 lck div 4
pck 42666666 pck div 1
- DSI1 PLL -
dsi pll source = dss_sys_clk
Fint 1920000 regn 20
CLKIN4DDR 929280000 regm 242
DSS_FCK (DSS_FCLK) 154880000 regm_dispc 6 (off)
DSS_FCK (DSS_FCLK) 103253333 regm_dsi 9 (off)
- DSI1 -
dsi fclk source = DSS_FCK (DSS_FCLK)
DSI_FCLK 170666666
DDR_CLK 232320000
TxByteClkHS 58080000
LP_CLK 12906666

* DSI registers Dump

DSI_REVISION 00000030
DSI_SYSCONFIG 00000015
DSI_SYSSTATUS 00000001
DSI_IRQSTATUS 000000a0
DSI_IRQENABLE 0015c000
DSI_CTRL 00eaee99
DSI_COMPLEXIO_CFG1 6a000321
DSI_COMPLEXIO_IRQ_STATUS 00000000
DSI_COMPLEXIO_IRQ_ENABLE 3ff07fff
DSI_CLK_CTRL a0346004
DSI_TIMING1 7fff7fff
DSI_TIMING2 ffff7fff
DSI_VM_TIMING1 001b900a
DSI_VM_TIMING2 04000318
DSI_VM_TIMING3 02eb02d0
DSI_CLK_TIMING 00001b11
DSI_TX_FIFO_VC_SIZE 13121110
DSI_RX_FIFO_VC_SIZE 13121110
DSI_COMPLEXIO_CFG2 00030000
DSI_RX_FIFO_VC_FULLNESS 00000000
DSI_VM_TIMING4 00487296
DSI_TX_FIFO_VC_EMPTINESS 1f1f001f
DSI_VM_TIMING5 0082df3b
DSI_VM_TIMING6 7a6731d1
DSI_VM_TIMING7 0012000f
DSI_STOPCLK_TIMING 00000080
DSI_VC_CTRL(0) 20808791
DSI_VC_TE(0) 00000000
DSI_VC_LONG_PACKET_HEADER(0) 00000000
DSI_VC_LONG_PACKET_PAYLOAD(0) 00000000
DSI_VC_SHORT_PACKET_HEADER(0) 00000000
DSI_VC_IRQSTATUS(0) 00000004
DSI_VC_IRQENABLE(0) 000000db
DSI_VC_CTRL(1) 20800f80
DSI_VC_TE(1) 00000000
DSI_VC_LONG_PACKET_HEADER(1) 00000000
DSI_VC_LONG_PACKET_PAYLOAD(1) 00000000
DSI_VC_SHORT_PACKET_HEADER(1) 00000000
DSI_VC_IRQSTATUS(1) 00000000
DSI_VC_IRQENABLE(1) 000000db
DSI_VC_CTRL(2) 20808d81
DSI_VC_TE(2) 00000000
DSI_VC_LONG_PACKET_HEADER(2) 00000000
DSI_VC_LONG_PACKET_PAYLOAD(2) 00000000
DSI_VC_SHORT_PACKET_HEADER(2) 00000000
DSI_VC_IRQSTATUS(2) 00000000
DSI_VC_IRQENABLE(2) 000000db
DSI_VC_CTRL(3) 20808d81
DSI_VC_TE(3) 00000000
DSI_VC_LONG_PACKET_HEADER(3) 00000000
DSI_VC_LONG_PACKET_PAYLOAD(3) 00000000
DSI_VC_SHORT_PACKET_HEADER(3) 00000000
DSI_VC_IRQSTATUS(3) 00000000
DSI_VC_IRQENABLE(3) 000000db
DSI_DSIPHY_CFG0 12291320
DSI_DSIPHY_CFG1 4206103a
DSI_DSIPHY_CFG2 b800000f
DSI_DSIPHY_CFG5 e7000000
DSI_PLL_CONTROL 00000000
DSI_PLL_STATUS 00000383
DSI_PLL_GO 00000000
DSI_PLL_CONFIGURATION1 20a1e427
DSI_PLL_CONFIGURATION2 00656008

*DISPC registers Dump

DISPC_REVISION 00000041
DISPC_SYSCONFIG 00002015
DISPC_SYSSTATUS 00000000
DISPC_IRQSTATUS 00000000
DISPC_IRQENABLE 0012d640
DISPC_CONTROL 00018308
DISPC_CONFIG 00020004
DISPC_CAPABLE 00000000
DISPC_DEFAULT_COLOR(OMAP_DSS_CHANNEL_LCD) 00000000
DISPC_DEFAULT_COLOR(OMAP_DSS_CHANNEL_DIGIT) 00000000
DISPC_TRANS_COLOR(OMAP_DSS_CHANNEL_LCD) 00000000
DISPC_TRANS_COLOR(OMAP_DSS_CHANNEL_DIGIT) 00000000
DISPC_LINE_STATUS 00000000
DISPC_LINE_NUMBER 00000000
DISPC_TIMING_H(OMAP_DSS_CHANNEL_LCD) 0130f208
DISPC_TIMING_V(OMAP_DSS_CHANNEL_LCD) 00400601
DISPC_POL_FREQ(OMAP_DSS_CHANNEL_LCD) 00000000
DISPC_DIVISORo(OMAP_DSS_CHANNEL_LCD) 00010004
DISPC_GLOBAL_ALPHA ffffffff
DISPC_SIZE_MGR(OMAP_DSS_CHANNEL_DIGIT) 00000000
DISPC_SIZE_MGR(OMAP_DSS_CHANNEL_LCD) 02cf04ff
DISPC_CONTROL2 00000000
DISPC_CONFIG2 00000000
DISPC_DEFAULT_COLOR(OMAP_DSS_CHANNEL_LCD2) 00000000
DISPC_TRANS_COLOR(OMAP_DSS_CHANNEL_LCD2) 00000000
DISPC_TIMING_H(OMAP_DSS_CHANNEL_LCD2) 00000000
DISPC_TIMING_V(OMAP_DSS_CHANNEL_LCD2) 00000000
DISPC_POL_FREQ(OMAP_DSS_CHANNEL_LCD2) 00000000
DISPC_DIVISORo(OMAP_DSS_CHANNEL_LCD2) 00040001
DISPC_SIZE_MGR(OMAP_DSS_CHANNEL_LCD2) 00000000
DISPC_OVL_BA0(OMAP_DSS_GFX) 7e40f800
DISPC_OVL_BA1(OMAP_DSS_GFX) 7e40f800
DISPC_OVL_POSITION(OMAP_DSS_GFX) 00260000
DISPC_OVL_SIZE(OMAP_DSS_GFX) 02a904ff
DISPC_OVL_ATTRIBUTES(OMAP_DSS_GFX) 02004090
DISPC_OVL_FIFO_THRESHOLD(OMAP_DSS_GFX) 04ff0270
DISPC_OVL_FIFO_SIZE_STATUS(OMAP_DSS_GFX) 00000500
DISPC_OVL_ROW_INC(OMAP_DSS_GFX) 00000001
DISPC_OVL_PIXEL_INC(OMAP_DSS_GFX) 00000001
DISPC_OVL_WINDOW_SKIP(OMAP_DSS_GFX) 00000000
DISPC_OVL_TABLE_BA(OMAP_DSS_GFX) 00000000
DISPC_DATA_CYCLE1(OMAP_DSS_CHANNEL_LCD) 00000000
DISPC_DATA_CYCLE2(OMAP_DSS_CHANNEL_LCD) 00000000
DISPC_DATA_CYCLE3(OMAP_DSS_CHANNEL_LCD) 00000000
DISPC_CPR_COEF_R(OMAP_DSS_CHANNEL_LCD) 00000000
DISPC_CPR_COEF_G(OMAP_DSS_CHANNEL_LCD) 00000000
DISPC_CPR_COEF_B(OMAP_DSS_CHANNEL_LCD) 00000000
DISPC_DATA_CYCLE1(OMAP_DSS_CHANNEL_LCD2) 00000000
DISPC_DATA_CYCLE2(OMAP_DSS_CHANNEL_LCD2) 00000000
DISPC_DATA_CYCLE3(OMAP_DSS_CHANNEL_LCD2) 00000000
DISPC_CPR_COEF_R(OMAP_DSS_CHANNEL_LCD2) 00000000
DISPC_CPR_COEF_G(OMAP_DSS_CHANNEL_LCD2) 00000000
DISPC_CPR_COEF_B(OMAP_DSS_CHANNEL_LCD2) 00000000
DISPC_OVL_PRELOAD(OMAP_DSS_GFX) 000004ff
DISPC_OVL_BA0(o) 7e793800
DISPC_OVL_BA1(o) 7e793800
DISPC_OVL_POSITION(o) 00260000
DISPC_OVL_SIZE(o) 02a904ff
DISPC_OVL_ATTRIBUTES(o) 16008018
DISPC_OVL_FIFO_THRESHOLD(o) 07ff0330
DISPC_OVL_FIFO_SIZE_STATUS(o) 00000800
DISPC_OVL_ROW_INC(o) 00000001
DISPC_OVL_PIXEL_INC(o) 00000001
DISPC_OVL_FIR(o) 04000400
DISPC_OVL_PICTURE_SIZE(o) 02a904ff
DISPC_OVL_ACCU0(o) 00000000
DISPC_OVL_ACCU1(o) 00000000
DISPC_OVL_FIR_COEF_H(o, i) 264c26f4
DISPC_OVL_FIR_COEF_H(o, i) 2f481ff2
DISPC_OVL_FIR_COEF_H(o, i) 354916f0
DISPC_OVL_FIR_COEF_H(o, i) 3b450ff0
DISPC_OVL_FIR_COEF_H(o, i) 08404008
DISPC_OVL_FIR_COEF_H(o, i) 0f453b01
DISPC_OVL_FIR_COEF_H(o, i) 164935fc
DISPC_OVL_FIR_COEF_H(o, i) 1f482ff7
DISPC_OVL_FIR_COEF_HV(o, i) 243824f4
DISPC_OVL_FIR_COEF_HV(o, i) 28391ff8
DISPC_OVL_FIR_COEF_HV(o, i) 2d381bfc
DISPC_OVL_FIR_COEF_HV(o, i) 32371701
DISPC_OVL_FIR_COEF_HV(o, i) 123737f0
DISPC_OVL_FIR_COEF_HV(o, i) 173732f0
DISPC_OVL_FIR_COEF_HV(o, i) 1b382df0
DISPC_OVL_FIR_COEF_HV(o, i) 1f3928f3
DISPC_OVL_CONV_COEF(o, i) 00000000
DISPC_OVL_CONV_COEF(o, i) 00000000
DISPC_OVL_CONV_COEF(o, i) 00000000
DISPC_OVL_CONV_COEF(o, i) 00000000
DISPC_OVL_CONV_COEF(o, i) 00000000
DISPC_OVL_FIR_COEF_V(o, i) 00000000
DISPC_OVL_FIR_COEF_V(o, i) 00000000
DISPC_OVL_FIR_COEF_V(o, i) 00000000
DISPC_OVL_FIR_COEF_V(o, i) 00000000
DISPC_OVL_FIR_COEF_V(o, i) 00000000
DISPC_OVL_FIR_COEF_V(o, i) 00000000
DISPC_OVL_FIR_COEF_V(o, i) 00000000
DISPC_OVL_FIR_COEF_V(o, i) 00000000
DISPC_OVL_BA0_UV(o) 00000000
DISPC_OVL_BA1_UV(o) 00000000
DISPC_OVL_FIR2(o) 04000400
DISPC_OVL_ACCU2_0(o) 00000000
DISPC_OVL_ACCU2_1(o) 00000000
DISPC_OVL_FIR_COEF_H2(o, i) 00000000
DISPC_OVL_FIR_COEF_H2(o, i) 00000000
DISPC_OVL_FIR_COEF_H2(o, i) 00000000
DISPC_OVL_FIR_COEF_H2(o, i) 00000000
DISPC_OVL_FIR_COEF_H2(o, i) 00000000
DISPC_OVL_FIR_COEF_H2(o, i) 00000000
DISPC_OVL_FIR_COEF_H2(o, i) 00000000
DISPC_OVL_FIR_COEF_H2(o, i) 00000000
DISPC_OVL_FIR_COEF_HV2(o, i) 00000000
DISPC_OVL_FIR_COEF_HV2(o, i) 00000000
DISPC_OVL_FIR_COEF_HV2(o, i) 00000000
DISPC_OVL_FIR_COEF_HV2(o, i) 00000000
DISPC_OVL_FIR_COEF_HV2(o, i) 00000000
DISPC_OVL_FIR_COEF_HV2(o, i) 00000000
DISPC_OVL_FIR_COEF_HV2(o, i) 00000000
DISPC_OVL_FIR_COEF_HV2(o, i) 00000000
DISPC_OVL_FIR_COEF_V2(o, i) 00000000
DISPC_OVL_FIR_COEF_V2(o, i) 00000000
DISPC_OVL_FIR_COEF_V2(o, i) 00000000
DISPC_OVL_FIR_COEF_V2(o, i) 00000000
DISPC_OVL_FIR_COEF_V2(o, i) 00000000
DISPC_OVL_FIR_COEF_V2(o, i) 00000000
DISPC_OVL_FIR_COEF_V2(o, i) 00000000
DISPC_OVL_FIR_COEF_V2(o, i) 00000000
DISPC_OVL_ATTRIBUTES2(o) 00000000
DISPC_OVL_PRELOAD(o) 000007ff
DISPC_OVL_BA0(o) 7eae8000
DISPC_OVL_BA1(o) 7eae8000
DISPC_OVL_POSITION(o) 00000000
DISPC_OVL_SIZE(o) 002504ff
DISPC_OVL_ATTRIBUTES(o) 1a008018
DISPC_OVL_FIFO_THRESHOLD(o) 07ff0330
DISPC_OVL_FIFO_SIZE_STATUS(o) 00000800
DISPC_OVL_ROW_INC(o) 00000001
DISPC_OVL_PIXEL_INC(o) 00000001
DISPC_OVL_FIR(o) 04000400
DISPC_OVL_PICTURE_SIZE(o) 002504ff
DISPC_OVL_ACCU0(o) 00000000
DISPC_OVL_ACCU1(o) 00000000
DISPC_OVL_FIR_COEF_H(o, i) 264c26f4
DISPC_OVL_FIR_COEF_H(o, i) 2f481ff2
DISPC_OVL_FIR_COEF_H(o, i) 354916f0
DISPC_OVL_FIR_COEF_H(o, i) 3b450ff0
DISPC_OVL_FIR_COEF_H(o, i) 08404008
DISPC_OVL_FIR_COEF_H(o, i) 0f453b01
DISPC_OVL_FIR_COEF_H(o, i) 164935fc
DISPC_OVL_FIR_COEF_H(o, i) 1f482ff7
DISPC_OVL_FIR_COEF_HV(o, i) 243824f4
DISPC_OVL_FIR_COEF_HV(o, i) 28391ff8
DISPC_OVL_FIR_COEF_HV(o, i) 2d381bfc
DISPC_OVL_FIR_COEF_HV(o, i) 32371701
DISPC_OVL_FIR_COEF_HV(o, i) 123737f0
DISPC_OVL_FIR_COEF_HV(o, i) 173732f0
DISPC_OVL_FIR_COEF_HV(o, i) 1b382df0
DISPC_OVL_FIR_COEF_HV(o, i) 1f3928f3
DISPC_OVL_CONV_COEF(o, i) 00000000
DISPC_OVL_CONV_COEF(o, i) 00000000
DISPC_OVL_CONV_COEF(o, i) 00000000
DISPC_OVL_CONV_COEF(o, i) 00000000
DISPC_OVL_CONV_COEF(o, i) 00000000
DISPC_OVL_FIR_COEF_V(o, i) 00000000
DISPC_OVL_FIR_COEF_V(o, i) 00000000
DISPC_OVL_FIR_COEF_V(o, i) 00000000
DISPC_OVL_FIR_COEF_V(o, i) 00000000
DISPC_OVL_FIR_COEF_V(o, i) 00000000
DISPC_OVL_FIR_COEF_V(o, i) 00000000
DISPC_OVL_FIR_COEF_V(o, i) 00000000
DISPC_OVL_FIR_COEF_V(o, i) 00000000
DISPC_OVL_BA0_UV(o) 00000000
DISPC_OVL_BA1_UV(o) 00000000
DISPC_OVL_FIR2(o) 04000400
DISPC_OVL_ACCU2_0(o) 00000000
DISPC_OVL_ACCU2_1(o) 00000000
DISPC_OVL_FIR_COEF_H2(o, i) 00000000
DISPC_OVL_FIR_COEF_H2(o, i) 00000000
DISPC_OVL_FIR_COEF_H2(o, i) 00000000
DISPC_OVL_FIR_COEF_H2(o, i) 00000000
DISPC_OVL_FIR_COEF_H2(o, i) 00000000
DISPC_OVL_FIR_COEF_H2(o, i) 00000000
DISPC_OVL_FIR_COEF_H2(o, i) 00000000
DISPC_OVL_FIR_COEF_H2(o, i) 00000000
DISPC_OVL_FIR_COEF_HV2(o, i) 00000000
DISPC_OVL_FIR_COEF_HV2(o, i) 00000000
DISPC_OVL_FIR_COEF_HV2(o, i) 00000000
DISPC_OVL_FIR_COEF_HV2(o, i) 00000000
DISPC_OVL_FIR_COEF_HV2(o, i) 00000000
DISPC_OVL_FIR_COEF_HV2(o, i) 00000000
DISPC_OVL_FIR_COEF_HV2(o, i) 00000000
DISPC_OVL_FIR_COEF_HV2(o, i) 00000000
DISPC_OVL_FIR_COEF_V2(o, i) 00000000
DISPC_OVL_FIR_COEF_V2(o, i) 00000000
DISPC_OVL_FIR_COEF_V2(o, i) 00000000
DISPC_OVL_FIR_COEF_V2(o, i) 00000000
DISPC_OVL_FIR_COEF_V2(o, i) 00000000
DISPC_OVL_FIR_COEF_V2(o, i) 00000000
DISPC_OVL_FIR_COEF_V2(o, i) 00000000
DISPC_OVL_FIR_COEF_V2(o, i) 00000000
DISPC_OVL_ATTRIBUTES2(o) 00000000
DISPC_OVL_PRELOAD(o) 000007ff
DISPC_OVL_BA0(o) 7eb18000
DISPC_OVL_BA1(o) 7eb18000
DISPC_OVL_POSITION(o) 00000000
DISPC_OVL_SIZE(o) 02cf04ff
DISPC_OVL_ATTRIBUTES(o) 1e008018
DISPC_OVL_FIFO_THRESHOLD(o) 07ff0330
DISPC_OVL_FIFO_SIZE_STATUS(o) 00000800
DISPC_OVL_ROW_INC(o) 00000001
DISPC_OVL_PIXEL_INC(o) 00000001
DISPC_OVL_FIR(o) 04000400
DISPC_OVL_PICTURE_SIZE(o) 02cf04ff
DISPC_OVL_ACCU0(o) 00000000
DISPC_OVL_ACCU1(o) 00000000
DISPC_OVL_FIR_COEF_H(o, i) 264c26f4
DISPC_OVL_FIR_COEF_H(o, i) 2f481ff2
DISPC_OVL_FIR_COEF_H(o, i) 354916f0
DISPC_OVL_FIR_COEF_H(o, i) 3b450ff0
DISPC_OVL_FIR_COEF_H(o, i) 08404008
DISPC_OVL_FIR_COEF_H(o, i) 0f453b01
DISPC_OVL_FIR_COEF_H(o, i) 164935fc
DISPC_OVL_FIR_COEF_H(o, i) 1f482ff7
DISPC_OVL_FIR_COEF_HV(o, i) 243824f4
DISPC_OVL_FIR_COEF_HV(o, i) 28391ff8
DISPC_OVL_FIR_COEF_HV(o, i) 2d381bfc
DISPC_OVL_FIR_COEF_HV(o, i) 32371701
DISPC_OVL_FIR_COEF_HV(o, i) 123737f0
DISPC_OVL_FIR_COEF_HV(o, i) 173732f0
DISPC_OVL_FIR_COEF_HV(o, i) 1b382df0
DISPC_OVL_FIR_COEF_HV(o, i) 1f3928f3
DISPC_OVL_CONV_COEF(o, i) 00000000
DISPC_OVL_CONV_COEF(o, i) 00000000
DISPC_OVL_CONV_COEF(o, i) 00000000
DISPC_OVL_CONV_COEF(o, i) 00000000
DISPC_OVL_CONV_COEF(o, i) 00000000
DISPC_OVL_FIR_COEF_V(o, i) 00000000
DISPC_OVL_FIR_COEF_V(o, i) 00000000
DISPC_OVL_FIR_COEF_V(o, i) 00000000
DISPC_OVL_FIR_COEF_V(o, i) 00000000
DISPC_OVL_FIR_COEF_V(o, i) 00000000
DISPC_OVL_FIR_COEF_V(o, i) 00000000
DISPC_OVL_FIR_COEF_V(o, i) 00000000
DISPC_OVL_FIR_COEF_V(o, i) 00000000
DISPC_OVL_BA0_UV(o) 00000000
DISPC_OVL_BA1_UV(o) 00000000
DISPC_OVL_FIR2(o) 04000400
DISPC_OVL_ACCU2_0(o) 00000000
DISPC_OVL_ACCU2_1(o) 00000000
DISPC_OVL_FIR_COEF_H2(o, i) 00000000
DISPC_OVL_FIR_COEF_H2(o, i) 00000000
DISPC_OVL_FIR_COEF_H2(o, i) 00000000
DISPC_OVL_FIR_COEF_H2(o, i) 00000000
DISPC_OVL_FIR_COEF_H2(o, i) 00000000
DISPC_OVL_FIR_COEF_H2(o, i) 00000000
DISPC_OVL_FIR_COEF_H2(o, i) 00000000
DISPC_OVL_FIR_COEF_H2(o, i) 00000000
DISPC_OVL_FIR_COEF_HV2(o, i) 00000000
DISPC_OVL_FIR_COEF_HV2(o, i) 00000000
DISPC_OVL_FIR_COEF_HV2(o, i) 00000000
DISPC_OVL_FIR_COEF_HV2(o, i) 00000000
DISPC_OVL_FIR_COEF_HV2(o, i) 00000000
DISPC_OVL_FIR_COEF_HV2(o, i) 00000000
DISPC_OVL_FIR_COEF_HV2(o, i) 00000000
DISPC_OVL_FIR_COEF_HV2(o, i) 00000000
DISPC_OVL_FIR_COEF_V2(o, i) 00000000
DISPC_OVL_FIR_COEF_V2(o, i) 00000000
DISPC_OVL_FIR_COEF_V2(o, i) 00000000
DISPC_OVL_FIR_COEF_V2(o, i) 00000000
DISPC_OVL_FIR_COEF_V2(o, i) 00000000
DISPC_OVL_FIR_COEF_V2(o, i) 00000000
DISPC_OVL_FIR_COEF_V2(o, i) 00000000
DISPC_OVL_FIR_COEF_V2(o, i) 00000000
DISPC_OVL_ATTRIBUTES2(o) 00000000
DISPC_OVL_PRELOAD(o) 000007ff

  • 0
    TI__Intellectual 1035 points

    Hi Wogee

    Yes. The DISPC and DSI timings need to match otherwise you get a resyncronization error. What software release are you using?

    I noticed two things:

    1. You are hardcoding the DSI blankings. On the file drivers/video/omap2/dss/dsi.c on line 3900 aprox it calculates them.
    2. What you say on the LCD panel specification doesn't match with DISPC blankings on the structure dispc_timings_tc35876x_hx7816. They should be the same. Which ones are you using? What does your datasheet says? Does it defines min, max and target values for the blankings?

    Please do not hardcode the DSI blankings or DSI.phy values and let the dsi.c driver calculate them, and let me know how do you do.

    Regards

    Rafael

     

  • 0 in reply to Rafael Rodriguez
    Prodigy 20 points

    Hi,

    Thanks  for your reply.

    I am using Blaze 4AJ.2.2 release.

    I know that dsi driver use panel's timings if  ".dispc_timings = NULL",.

    As you mentioned, if I set ".dispc_timings = NULL"  in my structure lcd_tc35876x_hx7816,  I got a resynchronization error.

    Also if I set ".dispc_timings = dispc_timings_tc35876x_hx7816",  I got a resynchronization error like as above.

    The value of dispc_timings_tc35876x_hx7816 and the value dispc_timings_tc35876x in your ref. source are same except resolution.

    My panel(HX7816) specification. ( 720P resolution is used in my custom board) 

     

    Regards,

    woogee