I'm working on a device that contains the TMS320C5515 DSP and a microprocessor using 8051 architecture. The plan is to use the UART of the 8051 and C5515 for inter-processor communication. Although I don't believe its common in most micros, the 8051 has a "9th" bit (transmitted after the 8 data bits) feature that we utilize to differentiate the 1st byte in a serial packet form the rest of the bytes in the packet. I believe it is independent of the parity bit.
I was hoping to try and configure the C5515 UART in a similar manner and ran across the "stick parity" option. It appears to be a way for me to force the parity bit to a certain state for a transmission. I can see utilizing this on a multi-byte packet transmission to the 8051. I'd simply force the bit high for my 1st byte, indicating a command byte, then force it low for the remaining bytes. I assume on both the C5515 transmission and reception of bytes, I will probably run into the parity error bit being set in the Line Status Register, but as long as the interrupt is disabled, I can ignore it.
I'm simply curious if anyone has tried to implement something similar or if there's something I'm overlooking in this configuration.
Thanks!
Adam