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I2S peripheral on ezdsp5535 in loopback mode

Hi,

I'm testing I2S2 on the ezdsp5535. I have it configured as a master, stereo, I2S mode, packed, 16-bit, with loopback enabled. For the moment, I'm polling the I2SINTFL. The data I read back from the RX data registers does not match what I'm transmitting. Sometimes the received data is correct, other times it appears to be delayed by one bit, other times it's not right at all. The clock runs at 1.536 MHz, 48-bits per frame, the FS is configured to run at 48 KHz. I've verified that the PLL is setup properly to support these settings.

When configured as packed, stereo, I2S mode, and servicing the data registers via the CPU, I write the left channel word to I2STXLT1 and the right channel word to I2STXLT0, and for receive, I read  the left word from I2SRXLT1 and the right word from I2SRXLT0. Is this correct, or am I missing something?

Thanks,

Jim

Sample code is below:

   hwI2SConfig.dataType           = I2S_STEREO_ENABLE;
    hwI2SConfig.loopBackMode       = I2S_LOOPBACK_ENABLE;
    hwI2SConfig.fsPol              = I2S_FSPOL_LOW;
    hwI2SConfig.clkPol             = I2S_RISING_EDGE;
    hwI2SConfig.datadelay          = I2S_DATADELAY_ONEBIT;
    hwI2SConfig.datapack           = I2S_DATAPACK_ENABLE;
    hwI2SConfig.signext            = I2S_SIGNEXT_DISABLE;
    hwI2SConfig.wordLen            = I2S_WORDLEN_16;
    hwI2SConfig.i2sMode            = I2S_MASTER;
    hwI2SConfig.dataFormat         = I2S_DATAFORMAT_LJUST;
    hwI2SConfig.fsDiv              = I2S_FSDIV32;
    hwI2SConfig.clkDiv             = I2S_CLKDIV64;
    hwI2SConfig.FError             = I2S_FSERROR_ENABLE;
    hwI2SConfig.OuError            = I2S_OUERROR_ENABLE;

    result += I2S_setup(hI2s, &hwI2SConfig);
    result += I2S_transEnable(hI2s, TRUE);
         for (i=0; i<32; i++) {
            rxL[i]  = 0;
            rxR[i] = 0;

                while((CSL_I2S_I2SINTFL_XMITSTFL_MASK & regs->I2SINTFL) == 0);  // Wait for transmit interrupt to be pending
                regs->I2STXLT1 = txL;    // 16 bit left channel transmit audio data
                regs->I2STXLT0 = txR;   // 16 bit left channel transmit audio data
            
                while((CSL_I2S_I2SINTFL_RCVSTFL_MASK & regs->I2SINTFL) == 0);  // Wait for receive interrupt to be pending
                rxL[i]  = regs->I2SRXLT1 ;  // 16 bit left channel receive audio data
                rxR[i]  = regs->I2SRXLT0 ;  // 16 bit left channel receive audio data
            
}