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C5505 CLKSTOP question

All:

In the documentation (SPRUGH5A) for powering down unused peripherals, the CLKSTOP register is used. Bits 1-0 in Figure 1-16 describe EMFCLKSTPACK and EMFCLKSTPREQ, but the Table 1-26 has Reserved in the Bit locations. I assume that C5505 uses these bits, but can someone tell me for sure whether they should be used when disabling the EMIF clock?

 

  • Hi Todd,

    This looks like a documentation error in Table 1-26 - bits 1 & 0 should not be reserved, and this is the correct way to stop the clocks to EMIF.

    It is important to request the clock stop if you have been using the peripheral to avoid potential device lock-up.

    See 1.5.3.2 Peripheral Domain Clock Gating in sprufx5d::

    If a peripheral's clock is stopped while being accessed, the access may not occur completely, and could potentially lock-up the device. To avoid this issue, some peripherals have a clock stop request and acknowledge protocol that allows software to ask the peripheral when it is safe to stop the clocks. This is described further in Section 1.5.3.2.2. For the peripherals that do not have the request/acknowledge protocol, the user must ensure that all of the transactions to the peripheral are finished prior to stopping the clocks.

    See 1.5.3.2.2 Peripheral Clock Stop Request/Acknowledge Register (CLKSTOP) [1C3Ah] in sprufx5d:

    You must execute a handshaking procedure before stopping the clock to the EMIF, USB, and UART. This handshake procedure ensures that current bus transactions are completed before the clock is stopped.
    The peripheral clock stop request/acknowledge register (CLKSTOP) enables this handshaking mechanism.

    To stop the clock to the EMIF, USB, or UART, set the corresponding clock stop request bit in the CLKSTOP register, then wait for the peripheral to set the corresponding clock stop acknowledge bit. Once
    this bit is set, you can idle the corresponding clock in the PCGCR1 and PCGCR2.

    To enable the clock to the EMIF, USB, or UART, first enable the clock the peripheral through PCGCR1 or PCGCR2, then clear the corresponding clock stop request bit in the CLKSTOP register.

    The peripheral clock stop request/acknowledge register (CLKSTOP) is shown in Figure 1-16 and described in Table 1-26.

    Hope this helps,
    Mark