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System Trace Clock frequency too high

Ralf Goebel
Genius 3715 points

Hello,

I'm using our custom hardware with a C6678 DSP, running at 1.25 GHz. I measured a frequency of about 104MHz for the System Trace Clock on the EMU0 pin. According to the Keyston Hardware Design Guide sprabi2b, the EMU signals can operate at up to 166Mbps. Because system trace uses DDR signaling, shouldn't the clock then be limited to 83MHz?

Changing the SYSCLK5 divider doesn't change trace clock frequency. But if I change the multiplier and reduce the core clock to 1.0GHz, the trace clock will also be reduced to 83MHz.

I originally posted this question in this forum, but it was moved to the CCS forum by a moderator and I'm getting no answer there:
http://e2e.ti.com/support/development_tools/code_composer_studio/f/81/t/242533.aspx

Thanks,
Ralf

  • 0
    TI__Mastermind 42545 points

    Hi Ralf,

    I would appear that there has been traffic on your original post.  Have your questions been answered? Can you tell me the procedure you went through to change the SYSCLK5 divider? Can you point to the description of trace using DDR signalling?

    Regards, Bill

  • 0 in reply to Bill Taboada
    Genius 3715 points

    Hi Bill,

    one different question was answered, but the frequency question is still not solved.

    The PLL divider PLLDIV5 is changed according to the PLL User Guide sprugv2e.

    The DDR signaling is mentioned in SPRU655I ("Emulation and Trace Headers"), section 10.

    Ralf

  • 0 in reply to Bill Taboada
    Genius 3715 points

    According to the original post, the maximum allowed data rate is 250 Mbps. The information in SPRABI2B (Keystone Hardware Design Guide => EMU signals max. 166 Mbps) and SPRS691C (C6678 Data Manual => SYSCLK5 max. 210 MHz) seems to be incorrect.

    Ralf