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Cycle difference between C55 and C6000

Robert W
Mastermind 7100 points

Hi,

I have a question about the SUBADD cycles of C55. I know some about C6000, but little about C55. They are quite different, but the difference is still a little too much than I expect. For C6000, memory read/write needs the most cycles (at least 4). Here C55 needs only one cycle for ADD/SUB a memory content. C55 has different DSP architecture with C6000. Its cycles need less, but the clock freqeuncy is rather slow?

I get the question because I write an algorithm for C6000 which originates from C55. The C6000 program cycle count is several times of that C55. I then notice that there is no penalty for memory access. I let compiler to optimize the linear assembly code. The improvement is not very much. I know delay slots can be utilized for other instructions to execute. Anyway, I cannot make the C6000 code cycle count near C55 within 2 times.

Is my observation true? What is your idea about the cycle count of C55 and C6000 generally?

 

Thanks,

 

 

 

SUBADD                         Dual 16-Bit Subtraction and Addition

Syntax Characteristics

No. Syntax        Parallel

                        Enable Bit                    Size                 Cycles              Pipeline

[1]                         No                              3                         1                      X

 

SUBADD Tx, Smem, ACx No 3 1 X

 

  • 0
    TI__Guru* 84285 points

    The C5500 and C6000 architectures are very different, as you've noted.  It's difficult to compare the relative speed of machines by looking at single instructions.

    Yes, C5500 has more complex instructions which can do more in a single instruction, so C5000 will generally beat C6000 in cycle count for single instructions, but C6000 more than makes up for this with a high degree of parallelism and higher clock cycle.  You need to look at the total microseconds to complete the algorithm.  If your code can be software pipelined, C6000 will. almost certainly beat C5500.