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I2S-DMA missing interrupts and overflow-framesync errors



Hi,

I’m trying to get I2S2 and DMA working on a ezDSP5535 board am reading I2S frame-sync and overflow errors every time the HW ISR executes (I2SINTFL = 0x0003).

The I2S is configured as: stereo, packed, 16-bit word, master, left-justified, 1-bit delay. The PLL is configured to run the CPU at 98.304 MHz. The I2S clock is divided by 64 to give 1.536 MHz. The I2S frame sync divides the clock by 32 to give a 48 KHz frame rate.

DMA controller1 configuration is: ping/pong, auto reload, channels 0 and 1 are synchronized to I2S Tx events. Channel 0 handles I2S Tx left transfers  channel 1 handles I2S Tx right transfers. DMA interrupts are only enabled for channel 1 (I2S right channel), as the I2S Tx sync event is triggered after the right-channel event occurs. The DMA interrupts occur after every 48 transfers – in theory, every 1 millisecond.

At the moment, no I2S Rx events are sync’d with DMA for debug purposes.

In my DMA HW ISR handler, I read the I2S INTFL register and also snapshot the current time with the BIOS CLK_gethtime(). I compute the delta-time between HW interrupts and save that info to a buffer. If  the ISRs were happening at exactly 1 ms, I would expect the delta-time to be 0xC000 every time. Instead I’m measuring delta values that indicate dropped interrupt events. The timing shows a periodicity to the HW interrupt timing – about 8 consecutive interrupts that are ‘close to’ 1 ms but still beyond what I expect, then about 5 consecutive interrupts where the delta time is on the order of 2 ms. This pattern can be seen in the memory snapshot below: each row shows three variables saved-off in during my ISR: the left column is delta-time from the last ISR, the middle column is the dmaifr event, and the third column is a global counter variable that is incremented from a periodic timer function that executes at a 1-ms rate. When the delta-time indicates a missing interrupt,  the global timer variable has incremented by 2.

The I2S2 CTRL register is programmed to 0x8092, ISSRATE register is programmed to 0x0015.

I’m at a loss as to what could be causing these timing fluctuations and missed interrupts. Does anyone have any suggestions?

Thanks,

Jim

0000BFD4    00000020    001DA604
0000BFCE    00000020    001DA605
0000BFBE    00000020    001DA606
0001B5F5    00000020    001DA608
00016FFD    00000020    001DA60A
0001A80C    00000020    001DA60C
000177FB    00000020    001DA60E
00016FFB    00000020    001DA610
0000BFCC    00000020    001DA611
0000BFC0    00000020    001DA612
0000BFD9    00000020    001DA613
0000C7C7    00000020    001DA614
0000C7C2    00000020    001DA615
0000BFD7    00000020    001DA616
0000C7C7    00000020    001DA617
0000C7C0    00000020    001DA618
0000BFDA    00000020    001DA619
000175DB    00000020    001DA61B
0001A811    00000020    001DA61E
000163FE    00000020    001DA61F
00016FFB    00000020    001DA621
000177F7    00000020    001DA623
0000FFCA    00000020    001DA625
0000C7D7    00000020    001DA626
0000C7CA    00000020    001DA627
0000C7BF    00000020    001DA628
0000BFD8    00000020    001DA629
0000C7C8    00000020    001DA62A
0000CFC0    00000020    001DA62B
0000BFD8    00000020    001DA62C
0000C7C7    00000020    001DA62D

  • Hi Jim,

    Sorry for the delay. This approach looks sound..

    Refer to the Audio Filter Demo code on http://code.google.com/p/c5505-ezdsp/

    This software does almost the same thing (not using latest CSL though).

    Can you provide code? What is the intermediate processing? SYSCLK? etc.

    Using BIOS? What is the utilization?

    Disregard first OUERROR that is generated per section 10.2.14.1 Initialization and Configuration Steps of the I2S User's Guide. Check your code sequence against this sequence.

    I beleive OUERR is generated if I2STXRT0/1 are not read by DMA or CPU - could try a dummy read.

    Try to disable FERR and OUERR and check for any missed DMA ISRs. Without seeing code cannot see effect of FERR and OUERR.

    Can you remove ping pong to simplify code as debugging step - is ping ping neccessary (block processing)?

    DMA memory allocated on 32-bit alignment?

    What is the I2S receive path?

    What happens at slower FS frequency?

    Regards,
    Mark