EDMA on DSP (DM3730) not working (NO OS)

Hi Natus,

As you can see the example source code at the link is for DM648 platform but you are using DM3730 therefore I recommend you to check are the addresses same for both platforms and if there are differences correct them.

BR

Tsvetolin Shulev

Hi,

There are address differences between both platforms and we made these changes. Is it possible that certain DMA logical channels can not be used or something is not enabled. We tried both external and L1D memories.

Thanks

Natus,

Can you check whether the EDMA3LLD package is getting compiled in your case? I've faced similar problems with DVSDK where the EDMA3LLD and framework components doesn't get compiled. 

To double check this, insert a compiler error inside code and see whether your build breaks or not. 

Hi,

We are not using EDMA3LLD package at all. We are writing directly to EDMA registers.

It has to be something trivial that we are missing.

Thanks

Hi Natus,

Is it possible to share your code snippet? I assume you are triggering EDMA from DSP.

Hi,
We tried few ways to get it working. Last attempt was just to use the sample code under the link given above. 

http://processors.wiki.ti.com/index.php/Programming_EDMA_without_EDMA3LLD_package

We just changed the addresses to match our processor.

Sample code is given below.

Thanks 

void dmaInit()
{
int i;

LogPrint("dmaInit()\n");

/* EDMA register address and definitions */

//#define EDMA_CC_BASE (0x02A00000) /* DM648. Check address for other devices. */
#define EDMA_CC_BASE (0x01C00000)
#define DCHMAP0 *((volatile unsigned int *)(EDMA_CC_BASE + 0x0100))
#define DMAQNUM0 *((volatile unsigned int *)(EDMA_CC_BASE + 0x0240))
#define QUEPRI *((volatile unsigned int *)(EDMA_CC_BASE + 0x0284))
#define EMCR *((volatile unsigned int *)(EDMA_CC_BASE + 0x0308))
#define EMCRH *((volatile unsigned int *)(EDMA_CC_BASE + 0x030C))
#define QEMCR *((volatile unsigned int *)(EDMA_CC_BASE + 0x0314))
#define CCERRCLR *((volatile unsigned int *)(EDMA_CC_BASE + 0x031C))
#define QWMTHRA *((volatile unsigned int *)(EDMA_CC_BASE + 0x0620))
#define ESR *((volatile unsigned int *)(EDMA_CC_BASE + 0x1010))
#define IPR *((volatile unsigned int *)(EDMA_CC_BASE + 0x1068))
#define ICR *((volatile unsigned int *)(EDMA_CC_BASE + 0x1070))

//#define PARAMENTRY0 (0x02A04000) /* DM648. Check address for other devices. */
#define PARAMENTRY0 (0x01C04000)
#define OPT *((volatile unsigned int *)(PARAMENTRY0 + 0x00))
#define SRC *((volatile unsigned int *)(PARAMENTRY0 + 0x04))
#define A_B_CNT *((volatile unsigned int *)(PARAMENTRY0 + 0x08))
#define DST *((volatile unsigned int *)(PARAMENTRY0 + 0x0C))
#define SRC_DST_BIDX *((volatile unsigned int *)(PARAMENTRY0 + 0x10))
#define LINK_BCNTRLD *((volatile unsigned int *)(PARAMENTRY0 + 0x14))
#define SRC_DST_CIDX *((volatile unsigned int *)(PARAMENTRY0 + 0x18))
#define CCNT *((volatile unsigned int *)(PARAMENTRY0 + 0x1C))

/* Allocate srcBuff and dstBuff. Do a cache flush and cache invalidate,if required. */
static signed char srcBuff[512];
static signed char dstBuff[512];

for(i=0;i<512;i++)
{
srcBuff[i] = i;
dstBuff[i] = 11;
}

/* Step 1: EDMA initialization */
QUEPRI=0x10;
QWMTHRA =(16<<8u)|(16 & 0xFF);
EMCR = 0xFFFFFFFF;
CCERRCLR = 0xFFFFFFFF;

/* Step 2: Programming DMA Channel (and Param set) */
DCHMAP0=0x0;
DMAQNUM0=0x0;
OPT = 0x00100000; /* only TCINTEN is set */
SRC = (unsigned int)srcBuff;
A_B_CNT = ((1 << 16u) | (512 & 0xFFFFu)); /* ACNT = 512, BCNT = 1 */
DST = (unsigned int)dstBuff;
SRC_DST_BIDX = (512 << 16u) | (512 & 0xFFFFu); /* SRC_BIDX = 512, DST_BIDX = 512 */
LINK_BCNTRLD = (1 << 16u) | 0xFFFFu; /* LINK = 0xFFFF, BCNTRLD = 1 */
SRC_DST_CIDX = 0;
CCNT = 1;

/* Step 3: Triggering the Transfer and Waiting for Transfer Completion */
//ESR = 0x1;
ESR = 0xFFFFFFFF;
while(((IPR) & 0x1) == 0);

/* Transfer has completed, clear the status register. */
ICR=0x01;

/* Transfer is complete. Compare the srcBuff and dstBuff */

LogPrint("\n");
LogPrint("dma_buff_src -- ");
for(i=0;i<16;i++)
{
LogPrint("%d ", srcBuff[i]);
}
LogPrint("\n");
LogPrint("dma_buff_dst -- ");
for(i=0;i<16;i++)
{
LogPrint("%d ", dstBuff[i]);
}
}

HI Natus,

Glad that it is working now...

Radhesh,

We did not get it working. I was just giving you an overview what we have done:)

Attached code is what you requested.

Thanks

HI Natus,

Apologies for misinterpreting your message. 

I have one question, is your code hanging at "while(((IPR) & 0x1) == 0);" or does it come out of this loop but there is no transfer happened?

Hi,

It comes out of the loop and prints out both buffer contents but the transfer does not happen.

Thanks

Hi Natus,

Sorry for responding late on this..as i was held up on some other tasks...

Did the EDMA work for you? 

If not, i might need answers for couple for more questions..

1. can you tell me the exact address of srcBuff and dstBuff? have you made sure that the addresses are accessible by EDMA?

2. Any reason for setting ESR = 0xFFFFFFFF ?

Hi,
EDMA is still not working. 

Below are the answers:

1. The addresses for scr and dst buffers are:

srcBuff - 0x8f164ca8
dstBuff - 0x8f164ea8

We also tried internal memory with the same result.
What addresses are accessible by EDMA?

2. This was just for debugging purposes. It should be ESR = 0x1; which we tried as well.

Thanks