tsip c6472 is not receiving data

Have you tried the TSIP digial loopback (DLB) example included in the C6472 CSL please? It may help you verify if the hardware setup is correct.

"\csl_c6472_03_00_07_01\csl_c6472\example\tsip\tsip_dlb_example\src\Tsip_dlb_example.c"

In your normal use case, please check if the data clock and frame sync clock are input correctly.

And could you elaborate what is the issue you are seeing please? 

Do you mean the transfer is working but it receives nothing? 

You probably could compare your test case with the TSIP example mentioned above to see if anything is missing. And it looks like you enable the TSIP interrupt in your source file, but the interrupt configuration file is not attached. Probably you would like to check if the interrupt in the DLB example could be reused in your case or needs any modification.

Hi Steven

TSIP digial loopback (DLB) example works is fine. Data clock and frame sync clock are input correctly. Harware setting evmc6472 revision 4, TDM0 - TSIP0_TX0, TDM1 - TSIP0_RX1, TDM2 - TSIP0_TX2, TDM3 - TSIP0_RX3. When transferring data buffer is filled correctly and issued correctly (TDM0 razistore 315). When you receive data buffer is filled with the values ​​0xFFFFFFFF on the whole length of the buffer. The project files are included   8321.my_tsip.rar  . Any help is appreciated.

Thanks

In your test setup, are you trying to loop the TX data back to RX through TDM externally or are the TX and RX data totally independent please?

If you are using external loopback, could you please check if the TX buffer underrun flag is set? Based on section "3.8.1 Transmit and Receive Synchronization" in TSIP user guide, the TDMU will send 0xFF to all enabled slot if there is no data available. 

If the TX and RX are independent, what is the expected data patter the RX buffer suppose to have please? 

I think in your channel bitmap configuration (e.g. xbitmapa0, rbitmapa0), TX and RX are enabling different time slots,  is it what you suppose to have please?